-- Xilinx Vhdl netlist produced by netgen application (version G.26)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim chnctrl.nga chnctrl_timesim.vhd 
-- Input file    : chnctrl.nga
-- Output file   : chnctrl_timesim.vhd
-- Design name   : chnctrl.nga
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : XC95144XL-5-TQ100 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity chnctrl is
  port (
    reset : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    acqen : in STD_LOGIC := 'X'; 
    full3 : in STD_LOGIC := 'X'; 
    trigmode : in STD_LOGIC := 'X'; 
    trigger : in STD_LOGIC := 'X'; 
    rstdataready : in STD_LOGIC := 'X'; 
    rst1 : out STD_LOGIC; 
    dataready : out STD_LOGIC; 
    dflag : out STD_LOGIC; 
    latchtrig : out STD_LOGIC; 
    ren1 : out STD_LOGIC; 
    ren2 : out STD_LOGIC; 
    rst2 : out STD_LOGIC; 
    rst3 : out STD_LOGIC; 
    wen1 : out STD_LOGIC; 
    wen2 : out STD_LOGIC; 
    wen3 : out STD_LOGIC; 
    dr : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    n1 : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end chnctrl;

architecture Structure of chnctrl is
  signal reset_IBUF : STD_LOGIC; 
  signal FSR_IO_2 : STD_LOGIC; 
  signal FCLKIO_0 : STD_LOGIC; 
  signal dr_0_IBUF : STD_LOGIC; 
  signal dr_1_IBUF : STD_LOGIC; 
  signal acqen_IBUF : STD_LOGIC; 
  signal full3_IBUF : STD_LOGIC; 
  signal trigmode_IBUF : STD_LOGIC; 
  signal FCLKIO_1 : STD_LOGIC; 
  signal n1_0_IBUF : STD_LOGIC; 
  signal rstdataready_IBUF : STD_LOGIC; 
  signal n1_1_IBUF : STD_LOGIC; 
  signal rst1_OBUF_Q : STD_LOGIC; 
  signal dataready_OBUF_Q : STD_LOGIC; 
  signal dflag_OBUF_Q : STD_LOGIC; 
  signal latchtrig_OBUF : STD_LOGIC; 
  signal ren1_OBUF_Q : STD_LOGIC; 
  signal ren2_OBUF : STD_LOGIC; 
  signal rst2_OBUF : STD_LOGIC; 
  signal rst3_OBUF : STD_LOGIC; 
  signal wen1_OBUF_Q : STD_LOGIC; 
  signal wen2_OBUF_Q : STD_LOGIC; 
  signal wen3_OBUF : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2 : STD_LOGIC; 
  signal EXP25_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_0 : STD_LOGIC; 
  signal EXP26_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_4_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_0 : STD_LOGIC; 
  signal EXP12_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_1 : STD_LOGIC; 
  signal EXP13_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_0_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_0 : STD_LOGIC; 
  signal EXP28_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_1 : STD_LOGIC; 
  signal EXP29_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_2_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_10_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_0 : STD_LOGIC; 
  signal EXP16_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_1 : STD_LOGIC; 
  signal EXP17_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_1_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_0 : STD_LOGIC; 
  signal EXP32_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_1 : STD_LOGIC; 
  signal EXP33_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_3_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2 : STD_LOGIC; 
  signal EXP22_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_0 : STD_LOGIC; 
  signal EXP23_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_5_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_6_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_7_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_D2 : STD_LOGIC; 
  signal EXP19_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_8_EXP_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_9_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo3_cnt_10_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_10_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_10_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_10_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_10_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_D2 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_3_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_4_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_4_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_4_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_4_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_5_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_5_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_5_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_5_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_PT_3 : STD_LOGIC; 
  signal Inst_fifo3_cnt_6_EXP_PT_4 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_PT_3 : STD_LOGIC; 
  signal Inst_fifo3_cnt_7_EXP_PT_4 : STD_LOGIC; 
  signal Inst_fifo3_cnt_8_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_8_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_8_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_8_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_8_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_9_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_9_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_9_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_9_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_9_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_RSTF : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D2 : STD_LOGIC; 
  signal rst1_OBUF : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_0_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_RSTF : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_1_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_RSTF : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_2_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_RSTF : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_3_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D2 : STD_LOGIC; 
  signal wen2_OBUF_EXP : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_SETF : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_1 : STD_LOGIC; 
  signal EXP18_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf2_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_RSTF : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_EXP_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_EXP_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_val_11_EXP_PT_2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_0_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_11_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_Q : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_D : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_RSTF : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_D1 : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_D2 : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_cnt_4_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_1_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_D : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_D1 : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_D2 : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_cnt_2_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_SETF : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D1 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_0 : STD_LOGIC; 
  signal EXP34_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_1 : STD_LOGIC; 
  signal EXP35_EXP : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_cnt_ovf1_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_Q : STD_LOGIC; 
  signal Inst_fifo3_ovf4096 : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_D : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_CE : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_D1 : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_D2 : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_ovf4096_D2_PT_1 : STD_LOGIC; 
  signal trigger_out_Q : STD_LOGIC; 
  signal trigger_out : STD_LOGIC; 
  signal trigger_out_RSTF : STD_LOGIC; 
  signal trigger_out_tsimcreated_prld_Q : STD_LOGIC; 
  signal trigger_out_D : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal trigger_out_CE : STD_LOGIC; 
  signal trigger_out_D1 : STD_LOGIC; 
  signal trigger_out_D2 : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout : STD_LOGIC; 
  signal trigger_out_trigger_out_RSTF_INT_UIM : STD_LOGIC; 
  signal rst1_OBUF_Q_0 : STD_LOGIC; 
  signal rst1_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal rst1_OBUF_D : STD_LOGIC; 
  signal rst1_OBUF_D1 : STD_LOGIC; 
  signal rst1_OBUF_D2 : STD_LOGIC; 
  signal rst1_OBUF_D2_PT_0 : STD_LOGIC; 
  signal rst1_OBUF_D2_PT_1 : STD_LOGIC; 
  signal dataready_OBUF_Q_1 : STD_LOGIC; 
  signal dataready_OBUF : STD_LOGIC; 
  signal dataready_OBUF_RSTF : STD_LOGIC; 
  signal dataready_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal dataready_OBUF_D : STD_LOGIC; 
  signal dataready_OBUF_CE : STD_LOGIC; 
  signal dataready_OBUF_D1 : STD_LOGIC; 
  signal dataready_OBUF_D2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT3_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2 : STD_LOGIC; 
  signal EXP20_EXP : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT2_D2_PT_5 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2_PT_3 : STD_LOGIC; 
  signal Inst_fifo2_state_FFT1_D2_PT_4 : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_Q : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_D : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_D1 : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_D2 : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo1_delay : STD_LOGIC; 
  signal Inst_fifo1_state_FFD2_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_Q : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D1 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D2 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D2_PT_1 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD2_D2_PT_2 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_Q : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_D : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_D1 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_D2 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_D2_PT_0 : STD_LOGIC; 
  signal Inst_fifo3_state_FFD1_D2_PT_1 : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_Q : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_RSTF : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_tsimcreated_prld_Q : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_D : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_CE : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_D1 : STD_LOGIC; 
  signal Inst_trigger_synch_trig_qout_D2 : STD_LOGIC; 
  signal Inst_fifo1_delay_Q : STD_LOGIC; 
  signal Inst_fifo1_delay_D : STD_LOGIC; 
  signal Inst_fifo1_delay_SETF : STD_LOGIC; 
  signal Inst_fifo1_delay_D1 : STD_LOGIC; 
  signal Inst_fifo1_delay_D2 : STD_LOGIC; 
  signal dflag_OBUF_Q_2 : STD_LOGIC; 
  signal dflag_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal dflag_OBUF_EXP : STD_LOGIC; 
  signal dflag_OBUF_D : STD_LOGIC; 
  signal dflag_OBUF_D1 : STD_LOGIC; 
  signal dflag_OBUF_D2 : STD_LOGIC; 
  signal dflag_OBUF_D2_PT_0 : STD_LOGIC; 
  signal dflag_OBUF_D2_PT_1 : STD_LOGIC; 
  signal dflag_OBUF_EXP_PT_0 : STD_LOGIC; 
  signal dflag_OBUF_EXP_PT_1 : STD_LOGIC; 
  signal latchtrig_OBUF_Q : STD_LOGIC; 
  signal latchtrig_OBUF_D : STD_LOGIC; 
  signal latchtrig_OBUF_D1 : STD_LOGIC; 
  signal latchtrig_OBUF_D2 : STD_LOGIC; 
  signal ren1_OBUF_Q_3 : STD_LOGIC; 
  signal ren1_OBUF_D : STD_LOGIC; 
  signal ren1_OBUF_D1 : STD_LOGIC; 
  signal ren1_OBUF_D2 : STD_LOGIC; 
  signal ren2_OBUF_Q : STD_LOGIC; 
  signal ren2_OBUF_D : STD_LOGIC; 
  signal ren2_OBUF_D1 : STD_LOGIC; 
  signal ren2_OBUF_D2 : STD_LOGIC; 
  signal ren2_OBUF_D2_PT_0 : STD_LOGIC; 
  signal ren2_OBUF_D2_PT_1 : STD_LOGIC; 
  signal ren2_OBUF_D2_PT_2 : STD_LOGIC; 
  signal ren2_OBUF_D2_PT_3 : STD_LOGIC; 
  signal ren2_OBUF_D2_PT_4 : STD_LOGIC; 
  signal rst2_OBUF_Q : STD_LOGIC; 
  signal rst2_OBUF_D : STD_LOGIC; 
  signal rst2_OBUF_D1 : STD_LOGIC; 
  signal rst2_OBUF_D2 : STD_LOGIC; 
  signal rst3_OBUF_Q : STD_LOGIC; 
  signal rst3_OBUF_D : STD_LOGIC; 
  signal rst3_OBUF_D1 : STD_LOGIC; 
  signal rst3_OBUF_D2 : STD_LOGIC; 
  signal wen1_OBUF_Q_4 : STD_LOGIC; 
  signal wen1_OBUF_tsimcreated_prld_Q : STD_LOGIC; 
  signal wen1_OBUF_D : STD_LOGIC; 
  signal wen1_OBUF_D1 : STD_LOGIC; 
  signal wen1_OBUF_D2 : STD_LOGIC; 
  signal wen1_OBUF_D2_PT_0 : STD_LOGIC; 
  signal wen1_OBUF_D2_PT_1 : STD_LOGIC; 
  signal wen2_OBUF_Q_5 : STD_LOGIC; 
  signal wen2_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal wen2_OBUF_D : STD_LOGIC; 
  signal wen2_OBUF_D1 : STD_LOGIC; 
  signal wen2_OBUF_D2 : STD_LOGIC; 
  signal wen3_OBUF_EXP : STD_LOGIC; 
  signal wen2_OBUF_D2_PT_0 : STD_LOGIC; 
  signal wen2_OBUF_D2_PT_1 : STD_LOGIC; 
  signal wen2_OBUF_D2_PT_2 : STD_LOGIC; 
  signal wen2_OBUF_D2_PT_3 : STD_LOGIC; 
  signal wen2_OBUF_EXP_PT_0 : STD_LOGIC; 
  signal wen2_OBUF_EXP_PT_1 : STD_LOGIC; 
  signal wen3_OBUF_Q : STD_LOGIC; 
  signal wen3_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal wen3_OBUF_D : STD_LOGIC; 
  signal wen3_OBUF_D1 : STD_LOGIC; 
  signal wen3_OBUF_D2 : STD_LOGIC; 
  signal wen3_OBUF_EXP_PT_0 : STD_LOGIC; 
  signal wen3_OBUF_EXP_PT_1 : STD_LOGIC; 
  signal wen3_OBUF_EXP_PT_2 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_Q : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_UIM : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D1 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2 : STD_LOGIC; 
  signal EXP10_EXP : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_0 : STD_LOGIC; 
  signal EXP11_EXP : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5 : STD_LOGIC; 
  signal Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6 : STD_LOGIC; 
  signal trigger_out_trigger_out_RSTF_INT_Q : STD_LOGIC; 
  signal trigger_out_trigger_out_RSTF_INT_D : STD_LOGIC; 
  signal trigger_out_trigger_out_RSTF_INT_D1 : STD_LOGIC; 
  signal trigger_out_trigger_out_RSTF_INT_D2 : STD_LOGIC; 
  signal EXP10_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP10_EXP_PT_0 : STD_LOGIC; 
  signal EXP10_EXP_PT_1 : STD_LOGIC; 
  signal EXP11_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP11_EXP_PT_0 : STD_LOGIC; 
  signal EXP11_EXP_PT_1 : STD_LOGIC; 
  signal EXP11_EXP_PT_2 : STD_LOGIC; 
  signal EXP11_EXP_PT_3 : STD_LOGIC; 
  signal EXP11_EXP_PT_4 : STD_LOGIC; 
  signal EXP12_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP12_EXP_PT_0 : STD_LOGIC; 
  signal EXP12_EXP_PT_1 : STD_LOGIC; 
  signal EXP12_EXP_PT_2 : STD_LOGIC; 
  signal EXP12_EXP_PT_3 : STD_LOGIC; 
  signal EXP12_EXP_PT_4 : STD_LOGIC; 
  signal EXP13_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP14_EXP : STD_LOGIC; 
  signal EXP13_EXP_PT_0 : STD_LOGIC; 
  signal EXP13_EXP_PT_1 : STD_LOGIC; 
  signal EXP13_EXP_PT_2 : STD_LOGIC; 
  signal EXP13_EXP_PT_3 : STD_LOGIC; 
  signal EXP13_EXP_PT_4 : STD_LOGIC; 
  signal EXP13_EXP_PT_5 : STD_LOGIC; 
  signal EXP14_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP14_EXP_PT_0 : STD_LOGIC; 
  signal EXP14_EXP_PT_1 : STD_LOGIC; 
  signal EXP14_EXP_PT_2 : STD_LOGIC; 
  signal EXP15_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP15_EXP : STD_LOGIC; 
  signal EXP15_EXP_PT_0 : STD_LOGIC; 
  signal EXP15_EXP_PT_1 : STD_LOGIC; 
  signal EXP15_EXP_PT_2 : STD_LOGIC; 
  signal EXP15_EXP_PT_3 : STD_LOGIC; 
  signal EXP15_EXP_PT_4 : STD_LOGIC; 
  signal EXP16_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP16_EXP_PT_0 : STD_LOGIC; 
  signal EXP16_EXP_PT_1 : STD_LOGIC; 
  signal EXP16_EXP_PT_2 : STD_LOGIC; 
  signal EXP16_EXP_PT_3 : STD_LOGIC; 
  signal EXP16_EXP_PT_4 : STD_LOGIC; 
  signal EXP16_EXP_PT_5 : STD_LOGIC; 
  signal EXP17_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP17_EXP_PT_0 : STD_LOGIC; 
  signal EXP17_EXP_PT_1 : STD_LOGIC; 
  signal EXP17_EXP_PT_2 : STD_LOGIC; 
  signal EXP17_EXP_PT_3 : STD_LOGIC; 
  signal EXP17_EXP_PT_4 : STD_LOGIC; 
  signal EXP18_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP18_EXP_PT_0 : STD_LOGIC; 
  signal EXP18_EXP_PT_1 : STD_LOGIC; 
  signal EXP18_EXP_PT_2 : STD_LOGIC; 
  signal EXP18_EXP_PT_3 : STD_LOGIC; 
  signal EXP18_EXP_PT_4 : STD_LOGIC; 
  signal EXP18_EXP_PT_5 : STD_LOGIC; 
  signal EXP19_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP19_EXP_PT_0 : STD_LOGIC; 
  signal EXP19_EXP_PT_1 : STD_LOGIC; 
  signal EXP19_EXP_PT_2 : STD_LOGIC; 
  signal EXP19_EXP_PT_3 : STD_LOGIC; 
  signal EXP19_EXP_PT_4 : STD_LOGIC; 
  signal EXP19_EXP_PT_5 : STD_LOGIC; 
  signal EXP20_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP21_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP21_EXP : STD_LOGIC; 
  signal EXP21_EXP_PT_0 : STD_LOGIC; 
  signal EXP21_EXP_PT_1 : STD_LOGIC; 
  signal EXP21_EXP_PT_2 : STD_LOGIC; 
  signal EXP22_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP22_EXP_PT_0 : STD_LOGIC; 
  signal EXP22_EXP_PT_1 : STD_LOGIC; 
  signal EXP22_EXP_PT_2 : STD_LOGIC; 
  signal EXP22_EXP_PT_3 : STD_LOGIC; 
  signal EXP22_EXP_PT_4 : STD_LOGIC; 
  signal EXP23_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP23_EXP_PT_0 : STD_LOGIC; 
  signal EXP23_EXP_PT_1 : STD_LOGIC; 
  signal EXP23_EXP_PT_2 : STD_LOGIC; 
  signal EXP23_EXP_PT_3 : STD_LOGIC; 
  signal EXP23_EXP_PT_4 : STD_LOGIC; 
  signal EXP23_EXP_PT_5 : STD_LOGIC; 
  signal EXP24_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP24_EXP : STD_LOGIC; 
  signal EXP24_EXP_PT_0 : STD_LOGIC; 
  signal EXP24_EXP_PT_1 : STD_LOGIC; 
  signal EXP24_EXP_PT_2 : STD_LOGIC; 
  signal EXP24_EXP_PT_3 : STD_LOGIC; 
  signal EXP24_EXP_PT_4 : STD_LOGIC; 
  signal EXP25_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP25_EXP_PT_0 : STD_LOGIC; 
  signal EXP25_EXP_PT_1 : STD_LOGIC; 
  signal EXP25_EXP_PT_2 : STD_LOGIC; 
  signal EXP25_EXP_PT_3 : STD_LOGIC; 
  signal EXP25_EXP_PT_4 : STD_LOGIC; 
  signal EXP25_EXP_PT_5 : STD_LOGIC; 
  signal EXP26_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP26_EXP_PT_0 : STD_LOGIC; 
  signal EXP26_EXP_PT_1 : STD_LOGIC; 
  signal EXP26_EXP_PT_2 : STD_LOGIC; 
  signal EXP26_EXP_PT_3 : STD_LOGIC; 
  signal EXP26_EXP_PT_4 : STD_LOGIC; 
  signal EXP27_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP27_EXP : STD_LOGIC; 
  signal EXP27_EXP_PT_0 : STD_LOGIC; 
  signal EXP27_EXP_PT_1 : STD_LOGIC; 
  signal EXP27_EXP_PT_2 : STD_LOGIC; 
  signal EXP28_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP28_EXP_PT_0 : STD_LOGIC; 
  signal EXP28_EXP_PT_1 : STD_LOGIC; 
  signal EXP28_EXP_PT_2 : STD_LOGIC; 
  signal EXP28_EXP_PT_3 : STD_LOGIC; 
  signal EXP28_EXP_PT_4 : STD_LOGIC; 
  signal EXP28_EXP_PT_5 : STD_LOGIC; 
  signal EXP29_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP30_EXP : STD_LOGIC; 
  signal EXP29_EXP_PT_0 : STD_LOGIC; 
  signal EXP29_EXP_PT_1 : STD_LOGIC; 
  signal EXP29_EXP_PT_2 : STD_LOGIC; 
  signal EXP29_EXP_PT_3 : STD_LOGIC; 
  signal EXP29_EXP_PT_4 : STD_LOGIC; 
  signal EXP29_EXP_PT_5 : STD_LOGIC; 
  signal EXP30_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP30_EXP_PT_0 : STD_LOGIC; 
  signal EXP30_EXP_PT_1 : STD_LOGIC; 
  signal EXP30_EXP_PT_2 : STD_LOGIC; 
  signal EXP30_EXP_PT_3 : STD_LOGIC; 
  signal EXP31_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP31_EXP : STD_LOGIC; 
  signal EXP31_EXP_PT_0 : STD_LOGIC; 
  signal EXP31_EXP_PT_1 : STD_LOGIC; 
  signal EXP31_EXP_PT_2 : STD_LOGIC; 
  signal EXP31_EXP_PT_3 : STD_LOGIC; 
  signal EXP31_EXP_PT_4 : STD_LOGIC; 
  signal EXP32_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP32_EXP_PT_0 : STD_LOGIC; 
  signal EXP32_EXP_PT_1 : STD_LOGIC; 
  signal EXP32_EXP_PT_2 : STD_LOGIC; 
  signal EXP32_EXP_PT_3 : STD_LOGIC; 
  signal EXP32_EXP_PT_4 : STD_LOGIC; 
  signal EXP32_EXP_PT_5 : STD_LOGIC; 
  signal EXP33_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP33_EXP_PT_0 : STD_LOGIC; 
  signal EXP33_EXP_PT_1 : STD_LOGIC; 
  signal EXP33_EXP_PT_2 : STD_LOGIC; 
  signal EXP33_EXP_PT_3 : STD_LOGIC; 
  signal EXP33_EXP_PT_4 : STD_LOGIC; 
  signal EXP33_EXP_PT_5 : STD_LOGIC; 
  signal EXP34_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP34_EXP_PT_0 : STD_LOGIC; 
  signal EXP34_EXP_PT_1 : STD_LOGIC; 
  signal EXP35_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP35_EXP_PT_0 : STD_LOGIC; 
  signal EXP35_EXP_PT_1 : STD_LOGIC; 
  signal EXP35_EXP_PT_2 : STD_LOGIC; 
  signal EXP35_EXP_PT_3 : STD_LOGIC; 
  signal EXP35_EXP_PT_4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_trigger_out_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_trigger_out_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_rst1_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_rst1_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_rst1_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dataready_OBUF_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dataready_OBUF_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dataready_OBUF_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dataready_OBUF_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_delay_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_delay_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_delay_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Inst_fifo1_delay_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_latchtrig_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_latchtrig_OBUF_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren1_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_ren2_OBUF_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_rst2_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_rst2_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_rst2_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_rst2_OBUF_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_rst3_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_rst3_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_rst3_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_wen1_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_wen1_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_wen1_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_wen1_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_wen2_OBUF_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP10_EXP_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_3_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP11_EXP_PT_4_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP12_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP13_EXP_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP14_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP14_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP15_EXP_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP17_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_4_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_5_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_2_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_3_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_4_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_4_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_4_IN0 : STD_LOGIC; 
  signal Inst_fifo2_Inst_ren_wen_Inst_decim_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Inst_fifo2_cnt_val : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Inst_fifo3_cnt : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Inst_fifo1_cnt : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  reset_IBUF_6 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF
    );
  FSR_IO_2_7 : X_INV
    port map (
      I => reset,
      O => FSR_IO_2
    );
  FCLKIO_0_8 : X_BUF
    port map (
      I => clk,
      O => FCLKIO_0
    );
  dr_0_IBUF_9 : X_BUF
    port map (
      I => dr(0),
      O => dr_0_IBUF
    );
  dr_1_IBUF_10 : X_BUF
    port map (
      I => dr(1),
      O => dr_1_IBUF
    );
  acqen_IBUF_11 : X_BUF
    port map (
      I => acqen,
      O => acqen_IBUF
    );
  full3_IBUF_12 : X_BUF
    port map (
      I => full3,
      O => full3_IBUF
    );
  trigmode_IBUF_13 : X_BUF
    port map (
      I => trigmode,
      O => trigmode_IBUF
    );
  FCLKIO_1_14 : X_BUF
    port map (
      I => trigger,
      O => FCLKIO_1
    );
  n1_0_IBUF_15 : X_BUF
    port map (
      I => n1(0),
      O => n1_0_IBUF
    );
  rstdataready_IBUF_16 : X_BUF
    port map (
      I => rstdataready,
      O => rstdataready_IBUF
    );
  n1_1_IBUF_17 : X_BUF
    port map (
      I => n1(1),
      O => n1_1_IBUF
    );
  rst1_18 : X_BUF
    port map (
      I => rst1_OBUF_Q,
      O => rst1
    );
  dataready_19 : X_BUF
    port map (
      I => dataready_OBUF_Q,
      O => dataready
    );
  dflag_20 : X_BUF
    port map (
      I => dflag_OBUF_Q,
      O => dflag
    );
  latchtrig_21 : X_BUF
    port map (
      I => latchtrig_OBUF,
      O => latchtrig
    );
  ren1_22 : X_BUF
    port map (
      I => ren1_OBUF_Q,
      O => ren1
    );
  ren2_23 : X_BUF
    port map (
      I => ren2_OBUF,
      O => ren2
    );
  rst2_24 : X_BUF
    port map (
      I => rst2_OBUF,
      O => rst2
    );
  rst3_25 : X_BUF
    port map (
      I => rst3_OBUF,
      O => rst3
    );
  wen1_26 : X_BUF
    port map (
      I => wen1_OBUF_Q,
      O => wen1
    );
  wen2_27 : X_BUF
    port map (
      I => wen2_OBUF_Q,
      O => wen2
    );
  wen3_28 : X_BUF
    port map (
      I => wen3_OBUF,
      O => wen3
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_Q_29 : X_BUF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0)
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_30 : X_BUF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q_31 : X_XOR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_REG : X_FF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_Q
    );
  Vcc_32 : X_ONE
    port map (
      O => Vcc
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D_33 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D1_34 : X_ZERO
    port map (
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_35 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN1,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_36 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_37 : X_OR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_38 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN4,
      I5 => Inst_fifo2_cnt_val(9),
      I6 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN6,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_39 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN4,
      I5 => Inst_fifo2_cnt_val(9),
      I6 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN7,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_40 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN4,
      I5 => Inst_fifo2_cnt_val(9),
      I6 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN7,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_tsimrenamed_net_Q_41 : X_OR3
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_tsimrenamed_net_Q
    );
  Inst_fifo2_cnt_val_4_Q_42 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_4_Q,
      O => Inst_fifo2_cnt_val(4)
    );
  Inst_fifo2_cnt_val_4_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_4_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_4_RSTF,
      O => Inst_fifo2_cnt_val_4_Q
    );
  Inst_fifo2_cnt_val_4_D_43 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_4_D1,
      I1 => Inst_fifo2_cnt_val_4_D2,
      O => Inst_fifo2_cnt_val_4_D
    );
  Inst_fifo2_cnt_val_4_D1_44 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_4_D1
    );
  Inst_fifo2_cnt_val_4_D2_PT_0_45 : X_AND2
    port map (
      I0 => EXP25_EXP,
      I1 => EXP25_EXP,
      O => Inst_fifo2_cnt_val_4_D2_PT_0
    );
  Inst_fifo2_cnt_val_4_D2_PT_1_46 : X_AND2
    port map (
      I0 => EXP26_EXP,
      I1 => EXP26_EXP,
      O => Inst_fifo2_cnt_val_4_D2_PT_1
    );
  Inst_fifo2_cnt_val_4_D2_PT_2_47 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN7,
      I8 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo2_cnt_val_4_D2_PT_2
    );
  Inst_fifo2_cnt_val_4_D2_PT_3_48 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN7,
      I8 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo2_cnt_val_4_D2_PT_3
    );
  Inst_fifo2_cnt_val_4_D2_PT_4_49 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN7,
      I8 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo2_cnt_val_4_D2_PT_4
    );
  Inst_fifo2_cnt_val_4_D2_PT_5_50 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN7,
      I8 => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo2_cnt_val_4_D2_PT_5
    );
  Inst_fifo2_cnt_val_4_D2_51 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_4_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_4_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_4_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_4_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_4_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_4_D2_PT_5,
      O => Inst_fifo2_cnt_val_4_D2
    );
  Inst_fifo2_cnt_val_4_RSTF_52 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN2,
      O => Inst_fifo2_cnt_val_4_RSTF
    );
  Inst_fifo2_cnt_val_0_Q_53 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_0_Q,
      O => Inst_fifo2_cnt_val(0)
    );
  Inst_fifo2_cnt_val_0_tsimcreated_xor_Q_54 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_0_D,
      I1 => Inst_fifo2_cnt_val_0_Q,
      O => Inst_fifo2_cnt_val_0_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_0_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_0_RSTF,
      O => Inst_fifo2_cnt_val_0_Q
    );
  Inst_fifo2_cnt_val_0_D_55 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D_IN0,
      I1 => Inst_fifo2_cnt_val_0_D2,
      O => Inst_fifo2_cnt_val_0_D
    );
  Inst_fifo2_cnt_val_0_D1_56 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_0_D1
    );
  Inst_fifo2_cnt_val_0_D2_PT_0_57 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_val_0_D2_PT_0
    );
  Inst_fifo2_cnt_val_0_D2_PT_1_58 : X_AND2
    port map (
      I0 => EXP12_EXP,
      I1 => EXP12_EXP,
      O => Inst_fifo2_cnt_val_0_D2_PT_1
    );
  Inst_fifo2_cnt_val_0_D2_PT_2_59 : X_AND2
    port map (
      I0 => EXP13_EXP,
      I1 => EXP13_EXP,
      O => Inst_fifo2_cnt_val_0_D2_PT_2
    );
  Inst_fifo2_cnt_val_0_D2_PT_3_60 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(10),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_val_0_D2_PT_3
    );
  Inst_fifo2_cnt_val_0_D2_PT_4_61 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(6),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_4_IN1,
      O => Inst_fifo2_cnt_val_0_D2_PT_4
    );
  Inst_fifo2_cnt_val_0_D2_PT_5_62 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(11),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_5_IN1,
      O => Inst_fifo2_cnt_val_0_D2_PT_5
    );
  Inst_fifo2_cnt_val_0_D2_63 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_0_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_0_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_0_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_0_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_0_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_0_D2_PT_5,
      O => Inst_fifo2_cnt_val_0_D2
    );
  Inst_fifo2_cnt_val_0_RSTF_64 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN2,
      O => Inst_fifo2_cnt_val_0_RSTF
    );
  Inst_fifo2_cnt_val_2_Q_65 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_2_Q,
      O => Inst_fifo2_cnt_val(2)
    );
  Inst_fifo2_cnt_val_2_tsimcreated_xor_Q_66 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_2_D,
      I1 => Inst_fifo2_cnt_val_2_Q,
      O => Inst_fifo2_cnt_val_2_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_2_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_2_RSTF,
      O => Inst_fifo2_cnt_val_2_Q
    );
  Inst_fifo2_cnt_val_2_D_67 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D_IN0,
      I1 => Inst_fifo2_cnt_val_2_D2,
      O => Inst_fifo2_cnt_val_2_D
    );
  Inst_fifo2_cnt_val_2_D1_68 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_2_D1
    );
  Inst_fifo2_cnt_val_2_D2_PT_0_69 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_val_2_D2_PT_0
    );
  Inst_fifo2_cnt_val_2_D2_PT_1_70 : X_AND2
    port map (
      I0 => EXP28_EXP,
      I1 => EXP28_EXP,
      O => Inst_fifo2_cnt_val_2_D2_PT_1
    );
  Inst_fifo2_cnt_val_2_D2_PT_2_71 : X_AND2
    port map (
      I0 => EXP29_EXP,
      I1 => EXP29_EXP,
      O => Inst_fifo2_cnt_val_2_D2_PT_2
    );
  Inst_fifo2_cnt_val_2_D2_PT_3_72 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(10),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_val_2_D2_PT_3
    );
  Inst_fifo2_cnt_val_2_D2_PT_4_73 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(6),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_4_IN1,
      O => Inst_fifo2_cnt_val_2_D2_PT_4
    );
  Inst_fifo2_cnt_val_2_D2_PT_5_74 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(11),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_5_IN1,
      O => Inst_fifo2_cnt_val_2_D2_PT_5
    );
  Inst_fifo2_cnt_val_2_D2_75 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_2_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_2_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_2_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_2_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_2_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_2_D2_PT_5,
      O => Inst_fifo2_cnt_val_2_D2
    );
  Inst_fifo2_cnt_val_2_RSTF_76 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN2,
      O => Inst_fifo2_cnt_val_2_RSTF
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_Q_77 : X_BUF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1)
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q_78 : X_XOR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_REG : X_FF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_Q
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D_79 : X_XOR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D1,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D1_80 : X_ZERO
    port map (
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_81 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_IN1,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_82 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => Inst_fifo2_state_FFT3,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_83 : X_OR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2
    );
  Inst_fifo2_cnt_val_10_Q_84 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_10_Q,
      O => Inst_fifo2_cnt_val(10)
    );
  Inst_fifo2_cnt_val_10_EXP_85 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_10_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_cnt_val_10_EXP
    );
  Inst_fifo2_cnt_val_10_tsimcreated_xor_Q_86 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_10_D,
      I1 => Inst_fifo2_cnt_val_10_Q,
      O => Inst_fifo2_cnt_val_10_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_10_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_10_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_10_RSTF,
      O => Inst_fifo2_cnt_val_10_Q
    );
  Inst_fifo2_cnt_val_10_D_87 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_10_D1,
      I1 => Inst_fifo2_cnt_val_10_D2,
      O => Inst_fifo2_cnt_val_10_D
    );
  Inst_fifo2_cnt_val_10_D1_88 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_10_D1
    );
  Inst_fifo2_cnt_val_10_D2_PT_0_89 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val_11_EXP,
      I1 => Inst_fifo2_cnt_val_11_EXP,
      O => Inst_fifo2_cnt_val_10_D2_PT_0
    );
  Inst_fifo2_cnt_val_10_D2_PT_1_90 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_10_D2_PT_1
    );
  Inst_fifo2_cnt_val_10_D2_PT_2_91 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_10_D2_PT_2
    );
  Inst_fifo2_cnt_val_10_D2_PT_3_92 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN5,
      I6 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_10_D2_PT_3
    );
  Inst_fifo2_cnt_val_10_D2_93 : X_OR4
    port map (
      I0 => Inst_fifo2_cnt_val_10_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_10_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_10_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_10_D2_PT_3,
      O => Inst_fifo2_cnt_val_10_D2
    );
  Inst_fifo2_cnt_val_10_RSTF_94 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN2,
      O => Inst_fifo2_cnt_val_10_RSTF
    );
  Inst_fifo2_cnt_val_10_EXP_tsimrenamed_net_Q_95 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_10_EXP_tsimrenamed_net_Q
    );
  Inst_fifo2_cnt_val_1_Q_96 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_1_Q,
      O => Inst_fifo2_cnt_val(1)
    );
  Inst_fifo2_cnt_val_1_tsimcreated_xor_Q_97 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_1_D,
      I1 => Inst_fifo2_cnt_val_1_Q,
      O => Inst_fifo2_cnt_val_1_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_1_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_1_RSTF,
      O => Inst_fifo2_cnt_val_1_Q
    );
  Inst_fifo2_cnt_val_1_D_98 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D_IN0,
      I1 => Inst_fifo2_cnt_val_1_D2,
      O => Inst_fifo2_cnt_val_1_D
    );
  Inst_fifo2_cnt_val_1_D1_99 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_1_D1
    );
  Inst_fifo2_cnt_val_1_D2_PT_0_100 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_val_1_D2_PT_0
    );
  Inst_fifo2_cnt_val_1_D2_PT_1_101 : X_AND2
    port map (
      I0 => EXP16_EXP,
      I1 => EXP16_EXP,
      O => Inst_fifo2_cnt_val_1_D2_PT_1
    );
  Inst_fifo2_cnt_val_1_D2_PT_2_102 : X_AND2
    port map (
      I0 => EXP17_EXP,
      I1 => EXP17_EXP,
      O => Inst_fifo2_cnt_val_1_D2_PT_2
    );
  Inst_fifo2_cnt_val_1_D2_PT_3_103 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(10),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_val_1_D2_PT_3
    );
  Inst_fifo2_cnt_val_1_D2_PT_4_104 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(6),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_4_IN1,
      O => Inst_fifo2_cnt_val_1_D2_PT_4
    );
  Inst_fifo2_cnt_val_1_D2_PT_5_105 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(11),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_5_IN1,
      O => Inst_fifo2_cnt_val_1_D2_PT_5
    );
  Inst_fifo2_cnt_val_1_D2_106 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_1_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_1_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_1_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_1_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_1_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_1_D2_PT_5,
      O => Inst_fifo2_cnt_val_1_D2
    );
  Inst_fifo2_cnt_val_1_RSTF_107 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN2,
      O => Inst_fifo2_cnt_val_1_RSTF
    );
  Inst_fifo2_cnt_val_3_Q_108 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_3_Q,
      O => Inst_fifo2_cnt_val(3)
    );
  Inst_fifo2_cnt_val_3_tsimcreated_xor_Q_109 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_3_D,
      I1 => Inst_fifo2_cnt_val_3_Q,
      O => Inst_fifo2_cnt_val_3_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_3_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_3_RSTF,
      O => Inst_fifo2_cnt_val_3_Q
    );
  Inst_fifo2_cnt_val_3_D_110 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D_IN0,
      I1 => Inst_fifo2_cnt_val_3_D2,
      O => Inst_fifo2_cnt_val_3_D
    );
  Inst_fifo2_cnt_val_3_D1_111 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_3_D1
    );
  Inst_fifo2_cnt_val_3_D2_PT_0_112 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_val_3_D2_PT_0
    );
  Inst_fifo2_cnt_val_3_D2_PT_1_113 : X_AND2
    port map (
      I0 => EXP32_EXP,
      I1 => EXP32_EXP,
      O => Inst_fifo2_cnt_val_3_D2_PT_1
    );
  Inst_fifo2_cnt_val_3_D2_PT_2_114 : X_AND2
    port map (
      I0 => EXP33_EXP,
      I1 => EXP33_EXP,
      O => Inst_fifo2_cnt_val_3_D2_PT_2
    );
  Inst_fifo2_cnt_val_3_D2_PT_3_115 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(10),
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_val_3_D2_PT_3
    );
  Inst_fifo2_cnt_val_3_D2_PT_4_116 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_4_IN0,
      I1 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_3_D2_PT_4
    );
  Inst_fifo2_cnt_val_3_D2_PT_5_117 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_5_IN0,
      I1 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_cnt_val_3_D2_PT_5
    );
  Inst_fifo2_cnt_val_3_D2_118 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_3_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_3_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_3_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_3_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_3_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_3_D2_PT_5,
      O => Inst_fifo2_cnt_val_3_D2
    );
  Inst_fifo2_cnt_val_3_RSTF_119 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN2,
      O => Inst_fifo2_cnt_val_3_RSTF
    );
  Inst_fifo2_cnt_val_5_Q_120 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_5_Q,
      O => Inst_fifo2_cnt_val(5)
    );
  Inst_fifo2_cnt_val_5_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_5_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_5_RSTF,
      O => Inst_fifo2_cnt_val_5_Q
    );
  Inst_fifo2_cnt_val_5_D_121 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_5_D1,
      I1 => Inst_fifo2_cnt_val_5_D2,
      O => Inst_fifo2_cnt_val_5_D
    );
  Inst_fifo2_cnt_val_5_D1_122 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_5_D1
    );
  Inst_fifo2_cnt_val_5_D2_PT_0_123 : X_AND2
    port map (
      I0 => EXP22_EXP,
      I1 => EXP22_EXP,
      O => Inst_fifo2_cnt_val_5_D2_PT_0
    );
  Inst_fifo2_cnt_val_5_D2_PT_1_124 : X_AND2
    port map (
      I0 => EXP23_EXP,
      I1 => EXP23_EXP,
      O => Inst_fifo2_cnt_val_5_D2_PT_1
    );
  Inst_fifo2_cnt_val_5_D2_PT_2_125 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      I3 => Inst_fifo2_cnt_val(5),
      O => Inst_fifo2_cnt_val_5_D2_PT_2
    );
  Inst_fifo2_cnt_val_5_D2_PT_3_126 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      I3 => Inst_fifo2_cnt_val(5),
      O => Inst_fifo2_cnt_val_5_D2_PT_3
    );
  Inst_fifo2_cnt_val_5_D2_PT_4_127 : X_AND5
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_4_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      I4 => Inst_fifo2_cnt_val(5),
      O => Inst_fifo2_cnt_val_5_D2_PT_4
    );
  Inst_fifo2_cnt_val_5_D2_PT_5_128 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN3,
      I4 => Inst_fifo2_cnt_val(5),
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN6,
      I7 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN7,
      I8 => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo2_cnt_val_5_D2_PT_5
    );
  Inst_fifo2_cnt_val_5_D2_129 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_val_5_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_5_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_5_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_5_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_5_D2_PT_4,
      I5 => Inst_fifo2_cnt_val_5_D2_PT_5,
      O => Inst_fifo2_cnt_val_5_D2
    );
  Inst_fifo2_cnt_val_5_RSTF_130 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN2,
      O => Inst_fifo2_cnt_val_5_RSTF
    );
  Inst_fifo2_cnt_val_6_Q_131 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_6_Q,
      O => Inst_fifo2_cnt_val(6)
    );
  Inst_fifo2_cnt_val_6_tsimcreated_xor_Q_132 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_6_D,
      I1 => Inst_fifo2_cnt_val_6_Q,
      O => Inst_fifo2_cnt_val_6_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_6_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_6_RSTF,
      O => Inst_fifo2_cnt_val_6_Q
    );
  Inst_fifo2_cnt_val_6_D_133 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_6_D1,
      I1 => Inst_fifo2_cnt_val_6_D2,
      O => Inst_fifo2_cnt_val_6_D
    );
  Inst_fifo2_cnt_val_6_D1_134 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_6_D1
    );
  Inst_fifo2_cnt_val_6_D2_PT_0_135 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val_7_EXP,
      I1 => Inst_fifo2_cnt_val_7_EXP,
      O => Inst_fifo2_cnt_val_6_D2_PT_0
    );
  Inst_fifo2_cnt_val_6_D2_PT_1_136 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_6_D2_PT_1
    );
  Inst_fifo2_cnt_val_6_D2_PT_2_137 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_6_D2_PT_2
    );
  Inst_fifo2_cnt_val_6_D2_PT_3_138 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN5,
      I6 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_6_D2_PT_3
    );
  Inst_fifo2_cnt_val_6_D2_PT_4_139 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN5,
      I6 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_6_D2_PT_4
    );
  Inst_fifo2_cnt_val_6_D2_140 : X_OR5
    port map (
      I0 => Inst_fifo2_cnt_val_6_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_6_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_6_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_6_D2_PT_3,
      I4 => Inst_fifo2_cnt_val_6_D2_PT_4,
      O => Inst_fifo2_cnt_val_6_D2
    );
  Inst_fifo2_cnt_val_6_RSTF_141 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN2,
      O => Inst_fifo2_cnt_val_6_RSTF
    );
  Inst_fifo2_cnt_val_7_Q_142 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_7_Q,
      O => Inst_fifo2_cnt_val(7)
    );
  Inst_fifo2_cnt_val_7_EXP_143 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_7_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_cnt_val_7_EXP
    );
  Inst_fifo2_cnt_val_7_tsimcreated_xor_Q_144 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_7_D,
      I1 => Inst_fifo2_cnt_val_7_Q,
      O => Inst_fifo2_cnt_val_7_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_7_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_7_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_7_RSTF,
      O => Inst_fifo2_cnt_val_7_Q
    );
  Inst_fifo2_cnt_val_7_D_145 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_7_D1,
      I1 => Inst_fifo2_cnt_val_7_D2,
      O => Inst_fifo2_cnt_val_7_D
    );
  Inst_fifo2_cnt_val_7_D1_146 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_7_D1
    );
  Inst_fifo2_cnt_val_7_D2_PT_0_147 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val_8_EXP,
      I1 => Inst_fifo2_cnt_val_8_EXP,
      O => Inst_fifo2_cnt_val_7_D2_PT_0
    );
  Inst_fifo2_cnt_val_7_D2_PT_1_148 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_7_D2_PT_1
    );
  Inst_fifo2_cnt_val_7_D2_PT_2_149 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_7_D2_PT_2
    );
  Inst_fifo2_cnt_val_7_D2_150 : X_OR3
    port map (
      I0 => Inst_fifo2_cnt_val_7_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_7_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_7_D2_PT_2,
      O => Inst_fifo2_cnt_val_7_D2
    );
  Inst_fifo2_cnt_val_7_RSTF_151 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN2,
      O => Inst_fifo2_cnt_val_7_RSTF
    );
  Inst_fifo2_cnt_val_7_EXP_PT_0_152 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN6,
      I7 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_7_EXP_PT_0
    );
  Inst_fifo2_cnt_val_7_EXP_PT_1_153 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN6,
      I7 => Inst_fifo2_cnt_val(6),
      O => Inst_fifo2_cnt_val_7_EXP_PT_1
    );
  Inst_fifo2_cnt_val_7_EXP_tsimrenamed_net_Q_154 : X_OR2
    port map (
      I0 => Inst_fifo2_cnt_val_7_EXP_PT_0,
      I1 => Inst_fifo2_cnt_val_7_EXP_PT_1,
      O => Inst_fifo2_cnt_val_7_EXP_tsimrenamed_net_Q
    );
  Inst_fifo2_cnt_val_8_Q_155 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_8_Q,
      O => Inst_fifo2_cnt_val(8)
    );
  Inst_fifo2_cnt_val_8_EXP_156 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_8_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_cnt_val_8_EXP
    );
  Inst_fifo2_cnt_val_8_tsimcreated_xor_Q_157 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_8_D,
      I1 => Inst_fifo2_cnt_val_8_Q,
      O => Inst_fifo2_cnt_val_8_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_8_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_8_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_8_RSTF,
      O => Inst_fifo2_cnt_val_8_Q
    );
  Inst_fifo2_cnt_val_8_D_158 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_8_D1,
      I1 => Inst_fifo2_cnt_val_8_D2,
      O => Inst_fifo2_cnt_val_8_D
    );
  Inst_fifo2_cnt_val_8_D1_159 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_8_D1
    );
  Inst_fifo2_cnt_val_8_D2_160 : X_AND2
    port map (
      I0 => EXP19_EXP,
      I1 => EXP19_EXP,
      O => Inst_fifo2_cnt_val_8_D2
    );
  Inst_fifo2_cnt_val_8_RSTF_161 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN2,
      O => Inst_fifo2_cnt_val_8_RSTF
    );
  Inst_fifo2_cnt_val_8_EXP_PT_0_162 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN5,
      I6 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_8_EXP_PT_0
    );
  Inst_fifo2_cnt_val_8_EXP_PT_1_163 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN5,
      I6 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_8_EXP_PT_1
    );
  Inst_fifo2_cnt_val_8_EXP_PT_2_164 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN6,
      I7 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_8_EXP_PT_2
    );
  Inst_fifo2_cnt_val_8_EXP_PT_3_165 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN6,
      I7 => Inst_fifo2_cnt_val(7),
      O => Inst_fifo2_cnt_val_8_EXP_PT_3
    );
  Inst_fifo2_cnt_val_8_EXP_tsimrenamed_net_Q_166 : X_OR4
    port map (
      I0 => Inst_fifo2_cnt_val_8_EXP_PT_0,
      I1 => Inst_fifo2_cnt_val_8_EXP_PT_1,
      I2 => Inst_fifo2_cnt_val_8_EXP_PT_2,
      I3 => Inst_fifo2_cnt_val_8_EXP_PT_3,
      O => Inst_fifo2_cnt_val_8_EXP_tsimrenamed_net_Q
    );
  Inst_fifo2_cnt_val_9_Q_167 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_9_Q,
      O => Inst_fifo2_cnt_val(9)
    );
  Inst_fifo2_cnt_val_9_EXP_168 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_cnt_val_9_EXP
    );
  Inst_fifo2_cnt_val_9_tsimcreated_xor_Q_169 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_9_D,
      I1 => Inst_fifo2_cnt_val_9_Q,
      O => Inst_fifo2_cnt_val_9_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_9_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_9_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_9_RSTF,
      O => Inst_fifo2_cnt_val_9_Q
    );
  Inst_fifo2_cnt_val_9_D_170 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_9_D1,
      I1 => Inst_fifo2_cnt_val_9_D2,
      O => Inst_fifo2_cnt_val_9_D
    );
  Inst_fifo2_cnt_val_9_D1_171 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_9_D1
    );
  Inst_fifo2_cnt_val_9_D2_PT_0_172 : X_AND2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP,
      O => Inst_fifo2_cnt_val_9_D2_PT_0
    );
  Inst_fifo2_cnt_val_9_D2_PT_1_173 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(9),
      O => Inst_fifo2_cnt_val_9_D2_PT_1
    );
  Inst_fifo2_cnt_val_9_D2_PT_2_174 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(9),
      O => Inst_fifo2_cnt_val_9_D2_PT_2
    );
  Inst_fifo2_cnt_val_9_D2_PT_3_175 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(9),
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN6,
      O => Inst_fifo2_cnt_val_9_D2_PT_3
    );
  Inst_fifo2_cnt_val_9_D2_176 : X_OR4
    port map (
      I0 => Inst_fifo2_cnt_val_9_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_9_D2_PT_1,
      I2 => Inst_fifo2_cnt_val_9_D2_PT_2,
      I3 => Inst_fifo2_cnt_val_9_D2_PT_3,
      O => Inst_fifo2_cnt_val_9_D2
    );
  Inst_fifo2_cnt_val_9_RSTF_177 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN2,
      O => Inst_fifo2_cnt_val_9_RSTF
    );
  Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_Q_178 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN6,
      I7 => Inst_fifo2_cnt_val(8),
      O => Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_Q
    );
  Inst_fifo3_cnt_10_Q_179 : X_BUF
    port map (
      I => Inst_fifo3_cnt_10_Q,
      O => Inst_fifo3_cnt(10)
    );
  Inst_fifo3_cnt_10_tsimcreated_xor_Q_180 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_10_D,
      I1 => Inst_fifo3_cnt_10_Q,
      O => Inst_fifo3_cnt_10_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_10_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_10_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_10_Q
    );
  Inst_fifo3_cnt_10_D_181 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_10_D1,
      I1 => Inst_fifo3_cnt_10_D2,
      O => Inst_fifo3_cnt_10_D
    );
  Inst_fifo3_cnt_10_D1_182 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_10_D1
    );
  Inst_fifo3_cnt_10_D2_183 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_10_D2
    );
  Inst_fifo3_cnt_3_Q_184 : X_BUF
    port map (
      I => Inst_fifo3_cnt_3_Q,
      O => Inst_fifo3_cnt(3)
    );
  Inst_fifo3_cnt_3_tsimcreated_xor_Q_185 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_3_D,
      I1 => Inst_fifo3_cnt_3_Q,
      O => Inst_fifo3_cnt_3_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_3_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_3_Q
    );
  Inst_fifo3_cnt_3_D_186 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_3_D1,
      I1 => Inst_fifo3_cnt_3_D2,
      O => Inst_fifo3_cnt_3_D
    );
  Inst_fifo3_cnt_3_D1_187 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_3_D1
    );
  Inst_fifo3_cnt_3_D2_PT_0_188 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN5,
      I6 => Inst_fifo3_cnt(0),
      I7 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN7,
      I8 => Inst_fifo3_cnt(1),
      I9 => Inst_fifo3_cnt(2),
      I10 => Inst_fifo3_state_FFD2,
      I11 => Inst_fifo3_state_FFD1,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_3_D2_PT_0
    );
  Inst_fifo3_cnt_3_D2_PT_1_189 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN4,
      I5 => Inst_fifo3_cnt(0),
      I6 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN6,
      I7 => Inst_fifo3_cnt(1),
      I8 => Inst_fifo3_cnt(2),
      I9 => Inst_fifo3_state_FFD2,
      I10 => Inst_fifo3_state_FFD1,
      I11 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN11,
      I12 => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN12,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_3_D2_PT_1
    );
  Inst_fifo3_cnt_3_D2_190 : X_OR2
    port map (
      I0 => Inst_fifo3_cnt_3_D2_PT_0,
      I1 => Inst_fifo3_cnt_3_D2_PT_1,
      O => Inst_fifo3_cnt_3_D2
    );
  Inst_fifo3_cnt_4_Q_191 : X_BUF
    port map (
      I => Inst_fifo3_cnt_4_Q,
      O => Inst_fifo3_cnt(4)
    );
  Inst_fifo3_cnt_4_tsimcreated_xor_Q_192 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_4_D,
      I1 => Inst_fifo3_cnt_4_Q,
      O => Inst_fifo3_cnt_4_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_4_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_4_Q
    );
  Inst_fifo3_cnt_4_D_193 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_4_D1,
      I1 => Inst_fifo3_cnt_4_D2,
      O => Inst_fifo3_cnt_4_D
    );
  Inst_fifo3_cnt_4_D1_194 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_4_D1
    );
  Inst_fifo3_cnt_4_D2_195 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN5,
      I6 => Inst_fifo3_cnt(0),
      I7 => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN7,
      I8 => Inst_fifo3_cnt(1),
      I9 => Inst_fifo3_cnt(2),
      I10 => Inst_fifo3_state_FFD2,
      I11 => Inst_fifo3_state_FFD1,
      I12 => Inst_fifo3_cnt(3),
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_4_D2
    );
  Inst_fifo3_cnt_5_Q_196 : X_BUF
    port map (
      I => Inst_fifo3_cnt_5_Q,
      O => Inst_fifo3_cnt(5)
    );
  Inst_fifo3_cnt_5_tsimcreated_xor_Q_197 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_5_D,
      I1 => Inst_fifo3_cnt_5_Q,
      O => Inst_fifo3_cnt_5_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_5_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_5_Q
    );
  Inst_fifo3_cnt_5_D_198 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_5_D1,
      I1 => Inst_fifo3_cnt_5_D2,
      O => Inst_fifo3_cnt_5_D
    );
  Inst_fifo3_cnt_5_D1_199 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_5_D1
    );
  Inst_fifo3_cnt_5_D2_200 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN5,
      I6 => Inst_fifo3_cnt(0),
      I7 => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN7,
      I8 => Inst_fifo3_cnt(1),
      I9 => Inst_fifo3_cnt(2),
      I10 => Inst_fifo3_state_FFD2,
      I11 => Inst_fifo3_state_FFD1,
      I12 => Inst_fifo3_cnt(3),
      I13 => Inst_fifo3_cnt(4),
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_5_D2
    );
  Inst_fifo3_cnt_6_Q_201 : X_BUF
    port map (
      I => Inst_fifo3_cnt_6_Q,
      O => Inst_fifo3_cnt(6)
    );
  Inst_fifo3_cnt_6_EXP_202 : X_BUF
    port map (
      I => Inst_fifo3_cnt_6_EXP_tsimrenamed_net_Q,
      O => Inst_fifo3_cnt_6_EXP
    );
  Inst_fifo3_cnt_6_tsimcreated_xor_Q_203 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_6_D,
      I1 => Inst_fifo3_cnt_6_Q,
      O => Inst_fifo3_cnt_6_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_6_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_6_Q
    );
  Inst_fifo3_cnt_6_D_204 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_6_D1,
      I1 => Inst_fifo3_cnt_6_D2,
      O => Inst_fifo3_cnt_6_D
    );
  Inst_fifo3_cnt_6_D1_205 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_6_D1
    );
  Inst_fifo3_cnt_6_D2_206 : X_AND2
    port map (
      I0 => Inst_fifo3_cnt_11_EXP,
      I1 => Inst_fifo3_cnt_11_EXP,
      O => Inst_fifo3_cnt_6_D2
    );
  Inst_fifo3_cnt_6_EXP_PT_0_207 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(9),
      I1 => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_0_IN1,
      O => Inst_fifo3_cnt_6_EXP_PT_0
    );
  Inst_fifo3_cnt_6_EXP_PT_1_208 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => Inst_fifo3_cnt_6_EXP_PT_1
    );
  Inst_fifo3_cnt_6_EXP_PT_2_209 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => Inst_fifo3_cnt_6_EXP_PT_2
    );
  Inst_fifo3_cnt_6_EXP_PT_3_210 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => Inst_fifo3_cnt_6_EXP_PT_3
    );
  Inst_fifo3_cnt_6_EXP_PT_4_211 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_4_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => Inst_fifo3_cnt_6_EXP_PT_4
    );
  Inst_fifo3_cnt_6_EXP_tsimrenamed_net_Q_212 : X_OR5
    port map (
      I0 => Inst_fifo3_cnt_6_EXP_PT_0,
      I1 => Inst_fifo3_cnt_6_EXP_PT_1,
      I2 => Inst_fifo3_cnt_6_EXP_PT_2,
      I3 => Inst_fifo3_cnt_6_EXP_PT_3,
      I4 => Inst_fifo3_cnt_6_EXP_PT_4,
      O => Inst_fifo3_cnt_6_EXP_tsimrenamed_net_Q
    );
  Inst_fifo3_cnt_7_Q_213 : X_BUF
    port map (
      I => Inst_fifo3_cnt_7_Q,
      O => Inst_fifo3_cnt(7)
    );
  Inst_fifo3_cnt_7_EXP_214 : X_BUF
    port map (
      I => Inst_fifo3_cnt_7_EXP_tsimrenamed_net_Q,
      O => Inst_fifo3_cnt_7_EXP
    );
  Inst_fifo3_cnt_7_tsimcreated_xor_Q_215 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_7_D,
      I1 => Inst_fifo3_cnt_7_Q,
      O => Inst_fifo3_cnt_7_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_7_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_7_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_7_Q
    );
  Inst_fifo3_cnt_7_D_216 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_7_D1,
      I1 => Inst_fifo3_cnt_7_D2,
      O => Inst_fifo3_cnt_7_D
    );
  Inst_fifo3_cnt_7_D1_217 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_7_D1
    );
  Inst_fifo3_cnt_7_D2_218 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val_10_EXP,
      I1 => Inst_fifo2_cnt_val_10_EXP,
      O => Inst_fifo3_cnt_7_D2
    );
  Inst_fifo3_cnt_7_EXP_PT_0_219 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(4),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_0_IN2,
      O => Inst_fifo3_cnt_7_EXP_PT_0
    );
  Inst_fifo3_cnt_7_EXP_PT_1_220 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(3),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_1_IN2,
      O => Inst_fifo3_cnt_7_EXP_PT_1
    );
  Inst_fifo3_cnt_7_EXP_PT_2_221 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_2_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => Inst_fifo3_cnt_7_EXP_PT_2
    );
  Inst_fifo3_cnt_7_EXP_PT_3_222 : X_AND8
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN6,
      I7 => Inst_fifo2_cnt_ovf2,
      O => Inst_fifo3_cnt_7_EXP_PT_3
    );
  Inst_fifo3_cnt_7_EXP_PT_4_223 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN6,
      I7 => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN7,
      I8 => Inst_fifo2_cnt_ovf2,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_7_EXP_PT_4
    );
  Inst_fifo3_cnt_7_EXP_tsimrenamed_net_Q_224 : X_OR5
    port map (
      I0 => Inst_fifo3_cnt_7_EXP_PT_0,
      I1 => Inst_fifo3_cnt_7_EXP_PT_1,
      I2 => Inst_fifo3_cnt_7_EXP_PT_2,
      I3 => Inst_fifo3_cnt_7_EXP_PT_3,
      I4 => Inst_fifo3_cnt_7_EXP_PT_4,
      O => Inst_fifo3_cnt_7_EXP_tsimrenamed_net_Q
    );
  Inst_fifo3_cnt_8_Q_225 : X_BUF
    port map (
      I => Inst_fifo3_cnt_8_Q,
      O => Inst_fifo3_cnt(8)
    );
  Inst_fifo3_cnt_8_tsimcreated_xor_Q_226 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_8_D,
      I1 => Inst_fifo3_cnt_8_Q,
      O => Inst_fifo3_cnt_8_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_8_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_8_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_8_Q
    );
  Inst_fifo3_cnt_8_D_227 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_8_D1,
      I1 => Inst_fifo3_cnt_8_D2,
      O => Inst_fifo3_cnt_8_D
    );
  Inst_fifo3_cnt_8_D1_228 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_8_D1
    );
  Inst_fifo3_cnt_8_D2_229 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_8_D2
    );
  Inst_fifo3_cnt_9_Q_230 : X_BUF
    port map (
      I => Inst_fifo3_cnt_9_Q,
      O => Inst_fifo3_cnt(9)
    );
  Inst_fifo3_cnt_9_tsimcreated_xor_Q_231 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_9_D,
      I1 => Inst_fifo3_cnt_9_Q,
      O => Inst_fifo3_cnt_9_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_9_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_9_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_9_Q
    );
  Inst_fifo3_cnt_9_D_232 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_9_D1,
      I1 => Inst_fifo3_cnt_9_D2,
      O => Inst_fifo3_cnt_9_D
    );
  Inst_fifo3_cnt_9_D1_233 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_9_D1
    );
  Inst_fifo3_cnt_9_D2_234 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_9_D2
    );
  Inst_fifo1_cnt_0_Q_235 : X_BUF
    port map (
      I => Inst_fifo1_cnt_0_Q,
      O => Inst_fifo1_cnt(0)
    );
  Inst_fifo1_cnt_0_tsimcreated_xor_Q_236 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_0_D,
      I1 => Inst_fifo1_cnt_0_Q,
      O => Inst_fifo1_cnt_0_tsimcreated_xor_Q
    );
  Inst_fifo1_cnt_0_REG : X_FF
    port map (
      I => Inst_fifo1_cnt_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo1_cnt_0_RSTF,
      O => Inst_fifo1_cnt_0_Q
    );
  Inst_fifo1_cnt_0_D_237 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_0_D_IN0,
      I1 => Inst_fifo1_cnt_0_D2,
      O => Inst_fifo1_cnt_0_D
    );
  Inst_fifo1_cnt_0_D1_238 : X_ZERO
    port map (
      O => Inst_fifo1_cnt_0_D1
    );
  Inst_fifo1_cnt_0_D2_PT_0_239 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN1,
      O => Inst_fifo1_cnt_0_D2_PT_0
    );
  Inst_fifo1_cnt_0_D2_PT_1_240 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_1_IN0,
      I1 => Inst_fifo1_state_FFD2,
      O => Inst_fifo1_cnt_0_D2_PT_1
    );
  Inst_fifo1_cnt_0_D2_PT_2_241 : X_AND6
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_2_IN1,
      I2 => Inst_fifo1_cnt(1),
      I3 => Inst_fifo1_cnt(2),
      I4 => Inst_fifo1_cnt(3),
      I5 => Inst_fifo1_cnt(4),
      O => Inst_fifo1_cnt_0_D2_PT_2
    );
  Inst_fifo1_cnt_0_D2_242 : X_OR3
    port map (
      I0 => Inst_fifo1_cnt_0_D2_PT_0,
      I1 => Inst_fifo1_cnt_0_D2_PT_1,
      I2 => Inst_fifo1_cnt_0_D2_PT_2,
      O => Inst_fifo1_cnt_0_D2
    );
  Inst_fifo1_cnt_0_RSTF_243 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN1,
      O => Inst_fifo1_cnt_0_RSTF
    );
  Inst_fifo1_cnt_1_Q_244 : X_BUF
    port map (
      I => Inst_fifo1_cnt_1_Q,
      O => Inst_fifo1_cnt(1)
    );
  Inst_fifo1_cnt_1_REG : X_FF
    port map (
      I => Inst_fifo1_cnt_1_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo1_cnt_1_RSTF,
      O => Inst_fifo1_cnt_1_Q
    );
  Inst_fifo1_cnt_1_D_245 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_1_D1,
      I1 => Inst_fifo1_cnt_1_D2,
      O => Inst_fifo1_cnt_1_D
    );
  Inst_fifo1_cnt_1_D1_246 : X_ZERO
    port map (
      O => Inst_fifo1_cnt_1_D1
    );
  Inst_fifo1_cnt_1_D2_PT_0_247 : X_AND4
    port map (
      I0 => Inst_fifo1_cnt(0),
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN3,
      O => Inst_fifo1_cnt_1_D2_PT_0
    );
  Inst_fifo1_cnt_1_D2_PT_1_248 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN0,
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN2,
      I3 => Inst_fifo1_cnt(1),
      O => Inst_fifo1_cnt_1_D2_PT_1
    );
  Inst_fifo1_cnt_1_D2_PT_2_249 : X_AND6
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_2_IN1,
      I2 => Inst_fifo1_cnt(1),
      I3 => Inst_fifo1_cnt(2),
      I4 => Inst_fifo1_cnt(3),
      I5 => Inst_fifo1_cnt(4),
      O => Inst_fifo1_cnt_1_D2_PT_2
    );
  Inst_fifo1_cnt_1_D2_250 : X_OR3
    port map (
      I0 => Inst_fifo1_cnt_1_D2_PT_0,
      I1 => Inst_fifo1_cnt_1_D2_PT_1,
      I2 => Inst_fifo1_cnt_1_D2_PT_2,
      O => Inst_fifo1_cnt_1_D2
    );
  Inst_fifo1_cnt_1_RSTF_251 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN1,
      O => Inst_fifo1_cnt_1_RSTF
    );
  Inst_fifo1_cnt_2_Q_252 : X_BUF
    port map (
      I => Inst_fifo1_cnt_2_Q,
      O => Inst_fifo1_cnt(2)
    );
  Inst_fifo1_cnt_2_REG : X_FF
    port map (
      I => Inst_fifo1_cnt_2_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo1_cnt_2_RSTF,
      O => Inst_fifo1_cnt_2_Q
    );
  Inst_fifo1_cnt_2_D_253 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_2_D1,
      I1 => Inst_fifo1_cnt_2_D2,
      O => Inst_fifo1_cnt_2_D
    );
  Inst_fifo1_cnt_2_D1_254 : X_ZERO
    port map (
      O => Inst_fifo1_cnt_2_D1
    );
  Inst_fifo1_cnt_2_D2_PT_0_255 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN0,
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN2,
      I3 => Inst_fifo1_cnt(2),
      O => Inst_fifo1_cnt_2_D2_PT_0
    );
  Inst_fifo1_cnt_2_D2_PT_1_256 : X_AND4
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN2,
      I3 => Inst_fifo1_cnt(2),
      O => Inst_fifo1_cnt_2_D2_PT_1
    );
  Inst_fifo1_cnt_2_D2_PT_2_257 : X_AND5
    port map (
      I0 => Inst_fifo1_cnt(0),
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN2,
      I3 => Inst_fifo1_cnt(1),
      I4 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN4,
      O => Inst_fifo1_cnt_2_D2_PT_2
    );
  Inst_fifo1_cnt_2_D2_PT_3_258 : X_AND5
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_3_IN1,
      I2 => Inst_fifo1_cnt(2),
      I3 => Inst_fifo1_cnt(3),
      I4 => Inst_fifo1_cnt(4),
      O => Inst_fifo1_cnt_2_D2_PT_3
    );
  Inst_fifo1_cnt_2_D2_259 : X_OR4
    port map (
      I0 => Inst_fifo1_cnt_2_D2_PT_0,
      I1 => Inst_fifo1_cnt_2_D2_PT_1,
      I2 => Inst_fifo1_cnt_2_D2_PT_2,
      I3 => Inst_fifo1_cnt_2_D2_PT_3,
      O => Inst_fifo1_cnt_2_D2
    );
  Inst_fifo1_cnt_2_RSTF_260 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN1,
      O => Inst_fifo1_cnt_2_RSTF
    );
  Inst_fifo1_cnt_3_Q_261 : X_BUF
    port map (
      I => Inst_fifo1_cnt_3_Q,
      O => Inst_fifo1_cnt(3)
    );
  Inst_fifo1_cnt_3_tsimcreated_xor_Q_262 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_3_D,
      I1 => Inst_fifo1_cnt_3_Q,
      O => Inst_fifo1_cnt_3_tsimcreated_xor_Q
    );
  Inst_fifo1_cnt_3_REG : X_FF
    port map (
      I => Inst_fifo1_cnt_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo1_cnt_3_RSTF,
      O => Inst_fifo1_cnt_3_Q
    );
  Inst_fifo1_cnt_3_D_263 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_3_D1,
      I1 => Inst_fifo1_cnt_3_D2,
      O => Inst_fifo1_cnt_3_D
    );
  Inst_fifo1_cnt_3_D1_264 : X_ZERO
    port map (
      O => Inst_fifo1_cnt_3_D1
    );
  Inst_fifo1_cnt_3_D2_PT_0_265 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_0_IN0,
      I1 => Inst_fifo1_cnt(3),
      O => Inst_fifo1_cnt_3_D2_PT_0
    );
  Inst_fifo1_cnt_3_D2_PT_1_266 : X_AND2
    port map (
      I0 => Inst_fifo1_state_FFD2,
      I1 => Inst_fifo1_cnt(3),
      O => Inst_fifo1_cnt_3_D2_PT_1
    );
  Inst_fifo1_cnt_3_D2_PT_2_267 : X_AND5
    port map (
      I0 => Inst_fifo1_cnt(0),
      I1 => Inst_fifo1_cnt(1),
      I2 => Inst_fifo1_cnt(2),
      I3 => Inst_fifo1_cnt(3),
      I4 => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_2_IN4,
      O => Inst_fifo1_cnt_3_D2_PT_2
    );
  Inst_fifo1_cnt_3_D2_PT_3_268 : X_AND6
    port map (
      I0 => Inst_fifo1_cnt(0),
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN2,
      I3 => Inst_fifo1_cnt(1),
      I4 => Inst_fifo1_cnt(2),
      I5 => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN5,
      O => Inst_fifo1_cnt_3_D2_PT_3
    );
  Inst_fifo1_cnt_3_D2_269 : X_OR4
    port map (
      I0 => Inst_fifo1_cnt_3_D2_PT_0,
      I1 => Inst_fifo1_cnt_3_D2_PT_1,
      I2 => Inst_fifo1_cnt_3_D2_PT_2,
      I3 => Inst_fifo1_cnt_3_D2_PT_3,
      O => Inst_fifo1_cnt_3_D2
    );
  Inst_fifo1_cnt_3_RSTF_270 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN1,
      O => Inst_fifo1_cnt_3_RSTF
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_Q_271 : X_BUF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2)
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_272 : X_BUF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q_273 : X_XOR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_Q,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_REG : X_FF
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_Q
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D_274 : X_XOR2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D1,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D2,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D1_275 : X_ZERO
    port map (
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D2_276 : X_AND2
    port map (
      I0 => wen2_OBUF_EXP,
      I1 => wen2_OBUF_EXP,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_D2
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0_277 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_278 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN5,
      I6 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_279 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN5,
      I6 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_280 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN6,
      I7 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_281 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN6,
      I7 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4
    );
  Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_tsimrenamed_net_Q_282 : X_OR5
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2,
      I3 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3,
      I4 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4,
      O => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_tsimrenamed_net_Q
    );
  Inst_fifo2_cnt_ovf2_283 : X_BUF
    port map (
      I => Inst_fifo2_cnt_ovf2_Q,
      O => Inst_fifo2_cnt_ovf2
    );
  Inst_fifo2_cnt_ovf2_tsimcreated_xor_Q_284 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_ovf2_D,
      I1 => Inst_fifo2_cnt_ovf2_Q,
      O => Inst_fifo2_cnt_ovf2_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_ovf2_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_ovf2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Inst_fifo2_cnt_ovf2_SETF,
      RST => PRLD,
      O => Inst_fifo2_cnt_ovf2_Q
    );
  Inst_fifo2_cnt_ovf2_D_285 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D_IN0,
      I1 => Inst_fifo2_cnt_ovf2_D2,
      O => Inst_fifo2_cnt_ovf2_D
    );
  Inst_fifo2_cnt_ovf2_D1_286 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_ovf2_D1
    );
  Inst_fifo2_cnt_ovf2_D2_PT_0_287 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_ovf2_D2_PT_0
    );
  Inst_fifo2_cnt_ovf2_D2_PT_1_288 : X_AND2
    port map (
      I0 => Inst_fifo3_cnt_6_EXP,
      I1 => Inst_fifo3_cnt_6_EXP,
      O => Inst_fifo2_cnt_ovf2_D2_PT_1
    );
  Inst_fifo2_cnt_ovf2_D2_PT_2_289 : X_AND2
    port map (
      I0 => EXP18_EXP,
      I1 => EXP18_EXP,
      O => Inst_fifo2_cnt_ovf2_D2_PT_2
    );
  Inst_fifo2_cnt_ovf2_D2_PT_3_290 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_ovf2_D2_PT_3
    );
  Inst_fifo2_cnt_ovf2_D2_PT_4_291 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN1,
      O => Inst_fifo2_cnt_ovf2_D2_PT_4
    );
  Inst_fifo2_cnt_ovf2_D2_PT_5_292 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN1,
      O => Inst_fifo2_cnt_ovf2_D2_PT_5
    );
  Inst_fifo2_cnt_ovf2_D2_293 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_ovf2_D2_PT_0,
      I1 => Inst_fifo2_cnt_ovf2_D2_PT_1,
      I2 => Inst_fifo2_cnt_ovf2_D2_PT_2,
      I3 => Inst_fifo2_cnt_ovf2_D2_PT_3,
      I4 => Inst_fifo2_cnt_ovf2_D2_PT_4,
      I5 => Inst_fifo2_cnt_ovf2_D2_PT_5,
      O => Inst_fifo2_cnt_ovf2_D2
    );
  Inst_fifo2_cnt_ovf2_SETF_294 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN2,
      O => Inst_fifo2_cnt_ovf2_SETF
    );
  Inst_fifo2_cnt_val_11_Q_295 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_11_Q,
      O => Inst_fifo2_cnt_val(11)
    );
  Inst_fifo2_cnt_val_11_EXP_296 : X_BUF
    port map (
      I => Inst_fifo2_cnt_val_11_EXP_tsimrenamed_net_Q,
      O => Inst_fifo2_cnt_val_11_EXP
    );
  Inst_fifo2_cnt_val_11_tsimcreated_xor_Q_297 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_11_D,
      I1 => Inst_fifo2_cnt_val_11_Q,
      O => Inst_fifo2_cnt_val_11_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_val_11_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_val_11_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo2_cnt_val_11_RSTF,
      O => Inst_fifo2_cnt_val_11_Q
    );
  Inst_fifo2_cnt_val_11_D_298 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_val_11_D1,
      I1 => Inst_fifo2_cnt_val_11_D2,
      O => Inst_fifo2_cnt_val_11_D
    );
  Inst_fifo2_cnt_val_11_D1_299 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_val_11_D1
    );
  Inst_fifo2_cnt_val_11_D2_PT_0_300 : X_AND2
    port map (
      I0 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP,
      O => Inst_fifo2_cnt_val_11_D2_PT_0
    );
  Inst_fifo2_cnt_val_11_D2_PT_1_301 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_Inst_fifo2_cnt_val_11_D2_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(11),
      O => Inst_fifo2_cnt_val_11_D2_PT_1
    );
  Inst_fifo2_cnt_val_11_D2_302 : X_OR2
    port map (
      I0 => Inst_fifo2_cnt_val_11_D2_PT_0,
      I1 => Inst_fifo2_cnt_val_11_D2_PT_1,
      O => Inst_fifo2_cnt_val_11_D2
    );
  Inst_fifo2_cnt_val_11_RSTF_303 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN2,
      O => Inst_fifo2_cnt_val_11_RSTF
    );
  Inst_fifo2_cnt_val_11_EXP_PT_0_304 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN5,
      I6 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_11_EXP_PT_0
    );
  Inst_fifo2_cnt_val_11_EXP_PT_1_305 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN6,
      I7 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_11_EXP_PT_1
    );
  Inst_fifo2_cnt_val_11_EXP_PT_2_306 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN6,
      I7 => Inst_fifo2_cnt_val(10),
      O => Inst_fifo2_cnt_val_11_EXP_PT_2
    );
  Inst_fifo2_cnt_val_11_EXP_tsimrenamed_net_Q_307 : X_OR3
    port map (
      I0 => Inst_fifo2_cnt_val_11_EXP_PT_0,
      I1 => Inst_fifo2_cnt_val_11_EXP_PT_1,
      I2 => Inst_fifo2_cnt_val_11_EXP_PT_2,
      O => Inst_fifo2_cnt_val_11_EXP_tsimrenamed_net_Q
    );
  Inst_fifo3_cnt_0_Q_308 : X_BUF
    port map (
      I => Inst_fifo3_cnt_0_Q,
      O => Inst_fifo3_cnt(0)
    );
  Inst_fifo3_cnt_0_tsimcreated_xor_Q_309 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_0_D,
      I1 => Inst_fifo3_cnt_0_Q,
      O => Inst_fifo3_cnt_0_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_0_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_0_Q
    );
  Inst_fifo3_cnt_0_D_310 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_0_D1,
      I1 => Inst_fifo3_cnt_0_D2,
      O => Inst_fifo3_cnt_0_D
    );
  Inst_fifo3_cnt_0_D1_311 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_0_D1
    );
  Inst_fifo3_cnt_0_D2_PT_0_312 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN5,
      I6 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN6,
      I7 => Inst_fifo3_state_FFD2,
      I8 => Inst_fifo3_state_FFD1,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_0_D2_PT_0
    );
  Inst_fifo3_cnt_0_D2_PT_1_313 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN5,
      I6 => Inst_fifo3_state_FFD2,
      I7 => Inst_fifo3_state_FFD1,
      I8 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN8,
      I9 => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_0_D2_PT_1
    );
  Inst_fifo3_cnt_0_D2_314 : X_OR2
    port map (
      I0 => Inst_fifo3_cnt_0_D2_PT_0,
      I1 => Inst_fifo3_cnt_0_D2_PT_1,
      O => Inst_fifo3_cnt_0_D2
    );
  Inst_fifo3_cnt_11_Q_315 : X_BUF
    port map (
      I => Inst_fifo3_cnt_11_Q,
      O => Inst_fifo3_cnt(11)
    );
  Inst_fifo3_cnt_11_EXP_316 : X_BUF
    port map (
      I => Inst_fifo3_cnt_11_EXP_tsimrenamed_net_Q,
      O => Inst_fifo3_cnt_11_EXP
    );
  Inst_fifo3_cnt_11_tsimcreated_xor_Q_317 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_11_D,
      I1 => Inst_fifo3_cnt_11_Q,
      O => Inst_fifo3_cnt_11_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_11_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_11_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_11_Q
    );
  Inst_fifo3_cnt_11_D_318 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_11_D1,
      I1 => Inst_fifo3_cnt_11_D2,
      O => Inst_fifo3_cnt_11_D
    );
  Inst_fifo3_cnt_11_D1_319 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_11_D1
    );
  Inst_fifo3_cnt_11_D2_320 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_11_D2
    );
  Inst_fifo3_cnt_11_EXP_tsimrenamed_net_Q_321 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_11_EXP_tsimrenamed_net_Q
    );
  Inst_fifo1_cnt_4_Q_322 : X_BUF
    port map (
      I => Inst_fifo1_cnt_4_Q,
      O => Inst_fifo1_cnt(4)
    );
  Inst_fifo1_cnt_4_REG : X_FF
    port map (
      I => Inst_fifo1_cnt_4_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Inst_fifo1_cnt_4_RSTF,
      O => Inst_fifo1_cnt_4_Q
    );
  Inst_fifo1_cnt_4_D_323 : X_XOR2
    port map (
      I0 => Inst_fifo1_cnt_4_D1,
      I1 => Inst_fifo1_cnt_4_D2,
      O => Inst_fifo1_cnt_4_D
    );
  Inst_fifo1_cnt_4_D1_324 : X_ZERO
    port map (
      O => Inst_fifo1_cnt_4_D1
    );
  Inst_fifo1_cnt_4_D2_PT_0_325 : X_AND3
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_0_IN1,
      I2 => Inst_fifo1_cnt(4),
      O => Inst_fifo1_cnt_4_D2_PT_0
    );
  Inst_fifo1_cnt_4_D2_PT_1_326 : X_AND6
    port map (
      I0 => Inst_fifo1_cnt(0),
      I1 => rst1_OBUF,
      I2 => NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_1_IN2,
      I3 => Inst_fifo1_cnt(1),
      I4 => Inst_fifo1_cnt(2),
      I5 => Inst_fifo1_cnt(3),
      O => Inst_fifo1_cnt_4_D2_PT_1
    );
  Inst_fifo1_cnt_4_D2_327 : X_OR2
    port map (
      I0 => Inst_fifo1_cnt_4_D2_PT_0,
      I1 => Inst_fifo1_cnt_4_D2_PT_1,
      O => Inst_fifo1_cnt_4_D2
    );
  Inst_fifo1_cnt_4_RSTF_328 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN1,
      O => Inst_fifo1_cnt_4_RSTF
    );
  Inst_fifo3_cnt_1_Q_329 : X_BUF
    port map (
      I => Inst_fifo3_cnt_1_Q,
      O => Inst_fifo3_cnt(1)
    );
  Inst_fifo3_cnt_1_tsimcreated_xor_Q_330 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_1_D,
      I1 => Inst_fifo3_cnt_1_Q,
      O => Inst_fifo3_cnt_1_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_1_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_1_Q
    );
  Inst_fifo3_cnt_1_D_331 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_1_D1,
      I1 => Inst_fifo3_cnt_1_D2,
      O => Inst_fifo3_cnt_1_D
    );
  Inst_fifo3_cnt_1_D1_332 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_1_D1
    );
  Inst_fifo3_cnt_1_D2_PT_0_333 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN5,
      I6 => Inst_fifo3_cnt(0),
      I7 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN7,
      I8 => Inst_fifo3_state_FFD2,
      I9 => Inst_fifo3_state_FFD1,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_1_D2_PT_0
    );
  Inst_fifo3_cnt_1_D2_PT_1_334 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN4,
      I5 => Inst_fifo3_cnt(0),
      I6 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN6,
      I7 => Inst_fifo3_state_FFD2,
      I8 => Inst_fifo3_state_FFD1,
      I9 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN9,
      I10 => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_1_D2_PT_1
    );
  Inst_fifo3_cnt_1_D2_335 : X_OR2
    port map (
      I0 => Inst_fifo3_cnt_1_D2_PT_0,
      I1 => Inst_fifo3_cnt_1_D2_PT_1,
      O => Inst_fifo3_cnt_1_D2
    );
  Inst_fifo3_cnt_2_Q_336 : X_BUF
    port map (
      I => Inst_fifo3_cnt_2_Q,
      O => Inst_fifo3_cnt(2)
    );
  Inst_fifo3_cnt_2_tsimcreated_xor_Q_337 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_2_D,
      I1 => Inst_fifo3_cnt_2_Q,
      O => Inst_fifo3_cnt_2_tsimcreated_xor_Q
    );
  Inst_fifo3_cnt_2_REG : X_FF
    port map (
      I => Inst_fifo3_cnt_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => FSR_IO_2,
      O => Inst_fifo3_cnt_2_Q
    );
  Inst_fifo3_cnt_2_D_338 : X_XOR2
    port map (
      I0 => Inst_fifo3_cnt_2_D1,
      I1 => Inst_fifo3_cnt_2_D2,
      O => Inst_fifo3_cnt_2_D
    );
  Inst_fifo3_cnt_2_D1_339 : X_ZERO
    port map (
      O => Inst_fifo3_cnt_2_D1
    );
  Inst_fifo3_cnt_2_D2_PT_0_340 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN5,
      I6 => Inst_fifo3_cnt(0),
      I7 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN7,
      I8 => Inst_fifo3_cnt(1),
      I9 => Inst_fifo3_state_FFD2,
      I10 => Inst_fifo3_state_FFD1,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_2_D2_PT_0
    );
  Inst_fifo3_cnt_2_D2_PT_1_341 : X_AND16
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN4,
      I5 => Inst_fifo3_cnt(0),
      I6 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN6,
      I7 => Inst_fifo3_cnt(1),
      I8 => Inst_fifo3_state_FFD2,
      I9 => Inst_fifo3_state_FFD1,
      I10 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN10,
      I11 => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN11,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Inst_fifo3_cnt_2_D2_PT_1
    );
  Inst_fifo3_cnt_2_D2_342 : X_OR2
    port map (
      I0 => Inst_fifo3_cnt_2_D2_PT_0,
      I1 => Inst_fifo3_cnt_2_D2_PT_1,
      O => Inst_fifo3_cnt_2_D2
    );
  Inst_fifo2_cnt_ovf1_343 : X_BUF
    port map (
      I => Inst_fifo2_cnt_ovf1_Q,
      O => Inst_fifo2_cnt_ovf1
    );
  Inst_fifo2_cnt_ovf1_tsimcreated_xor_Q_344 : X_XOR2
    port map (
      I0 => Inst_fifo2_cnt_ovf1_D,
      I1 => Inst_fifo2_cnt_ovf1_Q,
      O => Inst_fifo2_cnt_ovf1_tsimcreated_xor_Q
    );
  Inst_fifo2_cnt_ovf1_REG : X_FF
    port map (
      I => Inst_fifo2_cnt_ovf1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Inst_fifo2_cnt_ovf1_SETF,
      RST => PRLD,
      O => Inst_fifo2_cnt_ovf1_Q
    );
  Inst_fifo2_cnt_ovf1_D_345 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D_IN0,
      I1 => Inst_fifo2_cnt_ovf1_D2,
      O => Inst_fifo2_cnt_ovf1_D
    );
  Inst_fifo2_cnt_ovf1_D1_346 : X_ZERO
    port map (
      O => Inst_fifo2_cnt_ovf1_D1
    );
  Inst_fifo2_cnt_ovf1_D2_PT_0_347 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN1,
      O => Inst_fifo2_cnt_ovf1_D2_PT_0
    );
  Inst_fifo2_cnt_ovf1_D2_PT_1_348 : X_AND2
    port map (
      I0 => EXP34_EXP,
      I1 => EXP34_EXP,
      O => Inst_fifo2_cnt_ovf1_D2_PT_1
    );
  Inst_fifo2_cnt_ovf1_D2_PT_2_349 : X_AND2
    port map (
      I0 => EXP35_EXP,
      I1 => EXP35_EXP,
      O => Inst_fifo2_cnt_ovf1_D2_PT_2
    );
  Inst_fifo2_cnt_ovf1_D2_PT_3_350 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN1,
      O => Inst_fifo2_cnt_ovf1_D2_PT_3
    );
  Inst_fifo2_cnt_ovf1_D2_PT_4_351 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN1,
      O => Inst_fifo2_cnt_ovf1_D2_PT_4
    );
  Inst_fifo2_cnt_ovf1_D2_PT_5_352 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN1,
      O => Inst_fifo2_cnt_ovf1_D2_PT_5
    );
  Inst_fifo2_cnt_ovf1_D2_353 : X_OR6
    port map (
      I0 => Inst_fifo2_cnt_ovf1_D2_PT_0,
      I1 => Inst_fifo2_cnt_ovf1_D2_PT_1,
      I2 => Inst_fifo2_cnt_ovf1_D2_PT_2,
      I3 => Inst_fifo2_cnt_ovf1_D2_PT_3,
      I4 => Inst_fifo2_cnt_ovf1_D2_PT_4,
      I5 => Inst_fifo2_cnt_ovf1_D2_PT_5,
      O => Inst_fifo2_cnt_ovf1_D2
    );
  Inst_fifo2_cnt_ovf1_SETF_354 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN2,
      O => Inst_fifo2_cnt_ovf1_SETF
    );
  Inst_fifo3_ovf4096_355 : X_BUF
    port map (
      I => Inst_fifo3_ovf4096_Q,
      O => Inst_fifo3_ovf4096
    );
  Inst_fifo3_ovf4096_REG : X_FF
    port map (
      I => Inst_fifo3_ovf4096_D,
      CE => Inst_fifo3_ovf4096_CE,
      CLK => FCLKIO_0,
      SET => FSR_IO_2,
      RST => PRLD,
      O => Inst_fifo3_ovf4096_Q
    );
  Inst_fifo3_ovf4096_D_356 : X_XOR2
    port map (
      I0 => Inst_fifo3_ovf4096_D1,
      I1 => Inst_fifo3_ovf4096_D2,
      O => Inst_fifo3_ovf4096_D
    );
  Inst_fifo3_ovf4096_D1_357 : X_ZERO
    port map (
      O => Inst_fifo3_ovf4096_D1
    );
  Inst_fifo3_ovf4096_D2_PT_0_358 : X_AND7
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN5,
      I6 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN6,
      O => Inst_fifo3_ovf4096_D2_PT_0
    );
  Inst_fifo3_ovf4096_D2_PT_1_359 : X_AND8
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN1,
      I2 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN3,
      I4 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN4,
      I5 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN5,
      I6 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN6,
      I7 => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN7,
      O => Inst_fifo3_ovf4096_D2_PT_1
    );
  Inst_fifo3_ovf4096_D2_360 : X_OR2
    port map (
      I0 => Inst_fifo3_ovf4096_D2_PT_0,
      I1 => Inst_fifo3_ovf4096_D2_PT_1,
      O => Inst_fifo3_ovf4096_D2
    );
  Inst_fifo3_ovf4096_CE_361 : X_AND2
    port map (
      I0 => Inst_fifo3_state_FFD2,
      I1 => Inst_fifo3_state_FFD1,
      O => Inst_fifo3_ovf4096_CE
    );
  trigger_out_362 : X_BUF
    port map (
      I => trigger_out_Q,
      O => trigger_out
    );
  trigger_out_tsimcreated_prld_Q_363 : X_OR2
    port map (
      I0 => trigger_out_RSTF,
      I1 => PRLD,
      O => trigger_out_tsimcreated_prld_Q
    );
  trigger_out_REG : X_FF
    port map (
      I => trigger_out_D,
      CE => trigger_out_CE,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => trigger_out_tsimcreated_prld_Q,
      O => trigger_out_Q
    );
  Gnd_364 : X_ZERO
    port map (
      O => Gnd
    );
  trigger_out_D_365 : X_XOR2
    port map (
      I0 => trigger_out_D1,
      I1 => trigger_out_D2,
      O => trigger_out_D
    );
  trigger_out_D1_366 : X_ZERO
    port map (
      O => trigger_out_D1
    );
  trigger_out_D2_367 : X_AND2
    port map (
      I0 => Inst_trigger_synch_trig_qout,
      I1 => Inst_trigger_synch_trig_qout,
      O => trigger_out_D2
    );
  trigger_out_RSTF_368 : X_AND2
    port map (
      I0 => NlwInverterSignal_trigger_out_RSTF_IN0,
      I1 => NlwInverterSignal_trigger_out_RSTF_IN1,
      O => trigger_out_RSTF
    );
  trigger_out_CE_369 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => trigger_out_CE
    );
  rst1_OBUF_Q_370 : X_BUF
    port map (
      I => rst1_OBUF_Q_0,
      O => rst1_OBUF_Q
    );
  rst1_OBUF_371 : X_BUF
    port map (
      I => rst1_OBUF_Q_0,
      O => rst1_OBUF
    );
  rst1_OBUF_tsimcreated_prld_Q_372 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => rst1_OBUF_tsimcreated_prld_Q
    );
  rst1_OBUF_REG : X_FF
    port map (
      I => rst1_OBUF_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => rst1_OBUF_tsimcreated_prld_Q,
      O => rst1_OBUF_Q_0
    );
  rst1_OBUF_D_373 : X_XOR2
    port map (
      I0 => rst1_OBUF_D1,
      I1 => rst1_OBUF_D2,
      O => rst1_OBUF_D
    );
  rst1_OBUF_D1_374 : X_ZERO
    port map (
      O => rst1_OBUF_D1
    );
  rst1_OBUF_D2_PT_0_375 : X_AND3
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_rst1_OBUF_D2_PT_0_IN1,
      I2 => full3_IBUF,
      O => rst1_OBUF_D2_PT_0
    );
  rst1_OBUF_D2_PT_1_376 : X_AND3
    port map (
      I0 => NlwInverterSignal_rst1_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_rst1_OBUF_D2_PT_1_IN1,
      I2 => full3_IBUF,
      O => rst1_OBUF_D2_PT_1
    );
  rst1_OBUF_D2_377 : X_OR2
    port map (
      I0 => rst1_OBUF_D2_PT_0,
      I1 => rst1_OBUF_D2_PT_1,
      O => rst1_OBUF_D2
    );
  dataready_OBUF_Q_378 : X_BUF
    port map (
      I => dataready_OBUF_Q_1,
      O => dataready_OBUF_Q
    );
  dataready_OBUF_379 : X_BUF
    port map (
      I => dataready_OBUF_Q_1,
      O => dataready_OBUF
    );
  dataready_OBUF_tsimcreated_prld_Q_380 : X_OR2
    port map (
      I0 => dataready_OBUF_RSTF,
      I1 => PRLD,
      O => dataready_OBUF_tsimcreated_prld_Q
    );
  dataready_OBUF_REG : X_FF
    port map (
      I => dataready_OBUF_D,
      CE => dataready_OBUF_CE,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => dataready_OBUF_tsimcreated_prld_Q,
      O => dataready_OBUF_Q_1
    );
  dataready_OBUF_D_381 : X_XOR2
    port map (
      I0 => dataready_OBUF_D1,
      I1 => dataready_OBUF_D2,
      O => dataready_OBUF_D
    );
  dataready_OBUF_D1_382 : X_ZERO
    port map (
      O => dataready_OBUF_D1
    );
  dataready_OBUF_D2_383 : X_ONE
    port map (
      O => dataready_OBUF_D2
    );
  dataready_OBUF_RSTF_384 : X_AND2
    port map (
      I0 => NlwInverterSignal_dataready_OBUF_RSTF_IN0,
      I1 => NlwInverterSignal_dataready_OBUF_RSTF_IN1,
      O => dataready_OBUF_RSTF
    );
  dataready_OBUF_CE_385 : X_AND2
    port map (
      I0 => NlwInverterSignal_dataready_OBUF_CE_IN0,
      I1 => NlwInverterSignal_dataready_OBUF_CE_IN1,
      O => dataready_OBUF_CE
    );
  Inst_fifo2_state_FFT3_386 : X_BUF
    port map (
      I => Inst_fifo2_state_FFT3_Q,
      O => Inst_fifo2_state_FFT3
    );
  Inst_fifo2_state_FFT3_tsimcreated_prld_Q_387 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo2_state_FFT3_tsimcreated_prld_Q
    );
  Inst_fifo2_state_FFT3_REG : X_FF
    port map (
      I => Inst_fifo2_state_FFT3_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo2_state_FFT3_tsimcreated_prld_Q,
      O => Inst_fifo2_state_FFT3_Q
    );
  Inst_fifo2_state_FFT3_D_388 : X_XOR2
    port map (
      I0 => Inst_fifo2_state_FFT3_D1,
      I1 => Inst_fifo2_state_FFT3_D2,
      O => Inst_fifo2_state_FFT3_D
    );
  Inst_fifo2_state_FFT3_D1_389 : X_ZERO
    port map (
      O => Inst_fifo2_state_FFT3_D1
    );
  Inst_fifo2_state_FFT3_D2_PT_0_390 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN1,
      I2 => Inst_fifo2_state_FFT3,
      O => Inst_fifo2_state_FFT3_D2_PT_0
    );
  Inst_fifo2_state_FFT3_D2_PT_1_391 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT3,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_1_IN1,
      I2 => full3_IBUF,
      O => Inst_fifo2_state_FFT3_D2_PT_1
    );
  Inst_fifo2_state_FFT3_D2_PT_2_392 : X_AND6
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN1,
      I2 => rst1_OBUF,
      I3 => Inst_fifo1_state_FFD2,
      I4 => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN4,
      I5 => full3_IBUF,
      O => Inst_fifo2_state_FFT3_D2_PT_2
    );
  Inst_fifo2_state_FFT3_D2_393 : X_OR3
    port map (
      I0 => Inst_fifo2_state_FFT3_D2_PT_0,
      I1 => Inst_fifo2_state_FFT3_D2_PT_1,
      I2 => Inst_fifo2_state_FFT3_D2_PT_2,
      O => Inst_fifo2_state_FFT3_D2
    );
  Inst_fifo2_state_FFT2_394 : X_BUF
    port map (
      I => Inst_fifo2_state_FFT2_Q,
      O => Inst_fifo2_state_FFT2
    );
  Inst_fifo2_state_FFT2_tsimcreated_xor_Q_395 : X_XOR2
    port map (
      I0 => Inst_fifo2_state_FFT2_D,
      I1 => Inst_fifo2_state_FFT2_Q,
      O => Inst_fifo2_state_FFT2_tsimcreated_xor_Q
    );
  Inst_fifo2_state_FFT2_tsimcreated_prld_Q_396 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo2_state_FFT2_tsimcreated_prld_Q
    );
  Inst_fifo2_state_FFT2_REG : X_FF
    port map (
      I => Inst_fifo2_state_FFT2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo2_state_FFT2_tsimcreated_prld_Q,
      O => Inst_fifo2_state_FFT2_Q
    );
  Inst_fifo2_state_FFT2_D_397 : X_XOR2
    port map (
      I0 => Inst_fifo2_state_FFT2_D1,
      I1 => Inst_fifo2_state_FFT2_D2,
      O => Inst_fifo2_state_FFT2_D
    );
  Inst_fifo2_state_FFT2_D1_398 : X_ZERO
    port map (
      O => Inst_fifo2_state_FFT2_D1
    );
  Inst_fifo2_state_FFT2_D2_PT_0_399 : X_AND2
    port map (
      I0 => EXP20_EXP,
      I1 => EXP20_EXP,
      O => Inst_fifo2_state_FFT2_D2_PT_0
    );
  Inst_fifo2_state_FFT2_D2_PT_1_400 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => acqen_IBUF,
      O => Inst_fifo2_state_FFT2_D2_PT_1
    );
  Inst_fifo2_state_FFT2_D2_PT_2_401 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_2_IN1,
      O => Inst_fifo2_state_FFT2_D2_PT_2
    );
  Inst_fifo2_state_FFT2_D2_PT_3_402 : X_AND5
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => trigger_out,
      I4 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_3_IN4,
      O => Inst_fifo2_state_FFT2_D2_PT_3
    );
  Inst_fifo2_state_FFT2_D2_PT_4_403 : X_AND6
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN0,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN4,
      I5 => full3_IBUF,
      O => Inst_fifo2_state_FFT2_D2_PT_4
    );
  Inst_fifo2_state_FFT2_D2_PT_5_404 : X_AND6
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN3,
      I4 => full3_IBUF,
      I5 => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN5,
      O => Inst_fifo2_state_FFT2_D2_PT_5
    );
  Inst_fifo2_state_FFT2_D2_405 : X_OR6
    port map (
      I0 => Inst_fifo2_state_FFT2_D2_PT_0,
      I1 => Inst_fifo2_state_FFT2_D2_PT_1,
      I2 => Inst_fifo2_state_FFT2_D2_PT_2,
      I3 => Inst_fifo2_state_FFT2_D2_PT_3,
      I4 => Inst_fifo2_state_FFT2_D2_PT_4,
      I5 => Inst_fifo2_state_FFT2_D2_PT_5,
      O => Inst_fifo2_state_FFT2_D2
    );
  Inst_fifo2_state_FFT1_406 : X_BUF
    port map (
      I => Inst_fifo2_state_FFT1_Q,
      O => Inst_fifo2_state_FFT1
    );
  Inst_fifo2_state_FFT1_tsimcreated_xor_Q_407 : X_XOR2
    port map (
      I0 => Inst_fifo2_state_FFT1_D,
      I1 => Inst_fifo2_state_FFT1_Q,
      O => Inst_fifo2_state_FFT1_tsimcreated_xor_Q
    );
  Inst_fifo2_state_FFT1_tsimcreated_prld_Q_408 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo2_state_FFT1_tsimcreated_prld_Q
    );
  Inst_fifo2_state_FFT1_REG : X_FF
    port map (
      I => Inst_fifo2_state_FFT1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo2_state_FFT1_tsimcreated_prld_Q,
      O => Inst_fifo2_state_FFT1_Q
    );
  Inst_fifo2_state_FFT1_D_409 : X_XOR2
    port map (
      I0 => Inst_fifo2_state_FFT1_D1,
      I1 => Inst_fifo2_state_FFT1_D2,
      O => Inst_fifo2_state_FFT1_D
    );
  Inst_fifo2_state_FFT1_D1_410 : X_ZERO
    port map (
      O => Inst_fifo2_state_FFT1_D1
    );
  Inst_fifo2_state_FFT1_D2_PT_0_411 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => acqen_IBUF,
      O => Inst_fifo2_state_FFT1_D2_PT_0
    );
  Inst_fifo2_state_FFT1_D2_PT_1_412 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_1_IN1,
      O => Inst_fifo2_state_FFT1_D2_PT_1
    );
  Inst_fifo2_state_FFT1_D2_PT_2_413 : X_AND4
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN0,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN3,
      O => Inst_fifo2_state_FFT1_D2_PT_2
    );
  Inst_fifo2_state_FFT1_D2_PT_3_414 : X_AND6
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN3,
      I4 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN4,
      I5 => full3_IBUF,
      O => Inst_fifo2_state_FFT1_D2_PT_3
    );
  Inst_fifo2_state_FFT1_D2_PT_4_415 : X_AND6
    port map (
      I0 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN0,
      I1 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN1,
      I2 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN2,
      I3 => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN3,
      I4 => full3_IBUF,
      I5 => trigmode_IBUF,
      O => Inst_fifo2_state_FFT1_D2_PT_4
    );
  Inst_fifo2_state_FFT1_D2_416 : X_OR5
    port map (
      I0 => Inst_fifo2_state_FFT1_D2_PT_0,
      I1 => Inst_fifo2_state_FFT1_D2_PT_1,
      I2 => Inst_fifo2_state_FFT1_D2_PT_2,
      I3 => Inst_fifo2_state_FFT1_D2_PT_3,
      I4 => Inst_fifo2_state_FFT1_D2_PT_4,
      O => Inst_fifo2_state_FFT1_D2
    );
  Inst_fifo1_state_FFD2_417 : X_BUF
    port map (
      I => Inst_fifo1_state_FFD2_Q,
      O => Inst_fifo1_state_FFD2
    );
  Inst_fifo1_state_FFD2_tsimcreated_prld_Q_418 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo1_state_FFD2_tsimcreated_prld_Q
    );
  Inst_fifo1_state_FFD2_REG : X_FF
    port map (
      I => Inst_fifo1_state_FFD2_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo1_state_FFD2_tsimcreated_prld_Q,
      O => Inst_fifo1_state_FFD2_Q
    );
  Inst_fifo1_state_FFD2_D_419 : X_XOR2
    port map (
      I0 => Inst_fifo1_state_FFD2_D1,
      I1 => Inst_fifo1_state_FFD2_D2,
      O => Inst_fifo1_state_FFD2_D
    );
  Inst_fifo1_state_FFD2_D1_420 : X_ZERO
    port map (
      O => Inst_fifo1_state_FFD2_D1
    );
  Inst_fifo1_state_FFD2_D2_PT_0_421 : X_AND4
    port map (
      I0 => rst1_OBUF,
      I1 => Inst_fifo1_state_FFD2,
      I2 => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_0_IN2,
      I3 => full3_IBUF,
      O => Inst_fifo1_state_FFD2_D2_PT_0
    );
  Inst_fifo1_state_FFD2_D2_PT_1_422 : X_AND4
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN1,
      I2 => full3_IBUF,
      I3 => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN3,
      O => Inst_fifo1_state_FFD2_D2_PT_1
    );
  Inst_fifo1_state_FFD2_D2_423 : X_OR2
    port map (
      I0 => Inst_fifo1_state_FFD2_D2_PT_0,
      I1 => Inst_fifo1_state_FFD2_D2_PT_1,
      O => Inst_fifo1_state_FFD2_D2
    );
  Inst_fifo3_state_FFD2_424 : X_BUF
    port map (
      I => Inst_fifo3_state_FFD2_Q,
      O => Inst_fifo3_state_FFD2
    );
  Inst_fifo3_state_FFD2_tsimcreated_prld_Q_425 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo3_state_FFD2_tsimcreated_prld_Q
    );
  Inst_fifo3_state_FFD2_REG : X_FF
    port map (
      I => Inst_fifo3_state_FFD2_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo3_state_FFD2_tsimcreated_prld_Q,
      O => Inst_fifo3_state_FFD2_Q
    );
  Inst_fifo3_state_FFD2_D_426 : X_XOR2
    port map (
      I0 => Inst_fifo3_state_FFD2_D1,
      I1 => Inst_fifo3_state_FFD2_D2,
      O => Inst_fifo3_state_FFD2_D
    );
  Inst_fifo3_state_FFD2_D1_427 : X_ZERO
    port map (
      O => Inst_fifo3_state_FFD2_D1
    );
  Inst_fifo3_state_FFD2_D2_PT_0_428 : X_AND5
    port map (
      I0 => Inst_fifo3_state_FFD2,
      I1 => Inst_fifo3_state_FFD1,
      I2 => Inst_fifo3_ovf4096,
      I3 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_0_IN3,
      I4 => full3_IBUF,
      O => Inst_fifo3_state_FFD2_D2_PT_0
    );
  Inst_fifo3_state_FFD2_D2_PT_1_429 : X_AND7
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN3,
      I4 => Inst_fifo3_state_FFD1,
      I5 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN5,
      I6 => full3_IBUF,
      O => Inst_fifo3_state_FFD2_D2_PT_1
    );
  Inst_fifo3_state_FFD2_D2_PT_2_430 : X_AND7
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN0,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN3,
      I4 => Inst_fifo3_state_FFD1,
      I5 => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN5,
      I6 => full3_IBUF,
      O => Inst_fifo3_state_FFD2_D2_PT_2
    );
  Inst_fifo3_state_FFD2_D2_431 : X_OR3
    port map (
      I0 => Inst_fifo3_state_FFD2_D2_PT_0,
      I1 => Inst_fifo3_state_FFD2_D2_PT_1,
      I2 => Inst_fifo3_state_FFD2_D2_PT_2,
      O => Inst_fifo3_state_FFD2_D2
    );
  Inst_fifo3_state_FFD1_432 : X_BUF
    port map (
      I => Inst_fifo3_state_FFD1_Q,
      O => Inst_fifo3_state_FFD1
    );
  Inst_fifo3_state_FFD1_tsimcreated_prld_Q_433 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => Inst_fifo3_state_FFD1_tsimcreated_prld_Q
    );
  Inst_fifo3_state_FFD1_REG : X_FF
    port map (
      I => Inst_fifo3_state_FFD1_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => Inst_fifo3_state_FFD1_tsimcreated_prld_Q,
      O => Inst_fifo3_state_FFD1_Q
    );
  Inst_fifo3_state_FFD1_D_434 : X_XOR2
    port map (
      I0 => Inst_fifo3_state_FFD1_D1,
      I1 => Inst_fifo3_state_FFD1_D2,
      O => Inst_fifo3_state_FFD1_D
    );
  Inst_fifo3_state_FFD1_D1_435 : X_ZERO
    port map (
      O => Inst_fifo3_state_FFD1_D1
    );
  Inst_fifo3_state_FFD1_D2_PT_0_436 : X_AND3
    port map (
      I0 => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN1,
      I2 => full3_IBUF,
      O => Inst_fifo3_state_FFD1_D2_PT_0
    );
  Inst_fifo3_state_FFD1_D2_PT_1_437 : X_AND3
    port map (
      I0 => Inst_fifo3_state_FFD1,
      I1 => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_1_IN1,
      I2 => full3_IBUF,
      O => Inst_fifo3_state_FFD1_D2_PT_1
    );
  Inst_fifo3_state_FFD1_D2_438 : X_OR2
    port map (
      I0 => Inst_fifo3_state_FFD1_D2_PT_0,
      I1 => Inst_fifo3_state_FFD1_D2_PT_1,
      O => Inst_fifo3_state_FFD1_D2
    );
  Inst_trigger_synch_trig_qout_439 : X_BUF
    port map (
      I => Inst_trigger_synch_trig_qout_Q,
      O => Inst_trigger_synch_trig_qout
    );
  Inst_trigger_synch_trig_qout_tsimcreated_prld_Q_440 : X_OR2
    port map (
      I0 => Inst_trigger_synch_trig_qout_RSTF,
      I1 => PRLD,
      O => Inst_trigger_synch_trig_qout_tsimcreated_prld_Q
    );
  Inst_trigger_synch_trig_qout_REG : X_FF
    port map (
      I => Inst_trigger_synch_trig_qout_D,
      CE => Inst_trigger_synch_trig_qout_CE,
      CLK => FCLKIO_1,
      SET => Gnd,
      RST => Inst_trigger_synch_trig_qout_tsimcreated_prld_Q,
      O => Inst_trigger_synch_trig_qout_Q
    );
  Inst_trigger_synch_trig_qout_D_441 : X_XOR2
    port map (
      I0 => Inst_trigger_synch_trig_qout_D1,
      I1 => Inst_trigger_synch_trig_qout_D2,
      O => Inst_trigger_synch_trig_qout_D
    );
  Inst_trigger_synch_trig_qout_D1_442 : X_ZERO
    port map (
      O => Inst_trigger_synch_trig_qout_D1
    );
  Inst_trigger_synch_trig_qout_D2_443 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => Inst_trigger_synch_trig_qout_D2
    );
  Inst_trigger_synch_trig_qout_RSTF_444 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN0,
      I1 => NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN1,
      O => Inst_trigger_synch_trig_qout_RSTF
    );
  Inst_trigger_synch_trig_qout_CE_445 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => Inst_trigger_synch_trig_qout_CE
    );
  Inst_fifo1_delay_446 : X_BUF
    port map (
      I => Inst_fifo1_delay_Q,
      O => Inst_fifo1_delay
    );
  Inst_fifo1_delay_REG : X_FF
    port map (
      I => Inst_fifo1_delay_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Inst_fifo1_delay_SETF,
      RST => PRLD,
      O => Inst_fifo1_delay_Q
    );
  Inst_fifo1_delay_D_447 : X_XOR2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_delay_D_IN0,
      I1 => Inst_fifo1_delay_D2,
      O => Inst_fifo1_delay_D
    );
  Inst_fifo1_delay_D1_448 : X_ZERO
    port map (
      O => Inst_fifo1_delay_D1
    );
  Inst_fifo1_delay_D2_449 : X_AND6
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_Inst_fifo1_delay_D2_IN1,
      I2 => Inst_fifo1_cnt(1),
      I3 => Inst_fifo1_cnt(2),
      I4 => Inst_fifo1_cnt(3),
      I5 => Inst_fifo1_cnt(4),
      O => Inst_fifo1_delay_D2
    );
  Inst_fifo1_delay_SETF_450 : X_AND2
    port map (
      I0 => NlwInverterSignal_Inst_fifo1_delay_SETF_IN0,
      I1 => NlwInverterSignal_Inst_fifo1_delay_SETF_IN1,
      O => Inst_fifo1_delay_SETF
    );
  dflag_OBUF_Q_451 : X_BUF
    port map (
      I => dflag_OBUF_Q_2,
      O => dflag_OBUF_Q
    );
  dflag_OBUF_EXP_452 : X_BUF
    port map (
      I => dflag_OBUF_EXP_tsimrenamed_net_Q,
      O => dflag_OBUF_EXP
    );
  dflag_OBUF_Q_453 : X_BUF
    port map (
      I => dflag_OBUF_D,
      O => dflag_OBUF_Q_2
    );
  dflag_OBUF_D_454 : X_XOR2
    port map (
      I0 => dflag_OBUF_D1,
      I1 => dflag_OBUF_D2,
      O => dflag_OBUF_D
    );
  dflag_OBUF_D1_455 : X_ZERO
    port map (
      O => dflag_OBUF_D1
    );
  dflag_OBUF_D2_PT_0_456 : X_AND2
    port map (
      I0 => NlwInverterSignal_dflag_OBUF_D2_PT_0_IN0,
      I1 => Inst_fifo2_state_FFT3,
      O => dflag_OBUF_D2_PT_0
    );
  dflag_OBUF_D2_PT_1_457 : X_AND2
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => NlwInverterSignal_dflag_OBUF_D2_PT_1_IN1,
      O => dflag_OBUF_D2_PT_1
    );
  dflag_OBUF_D2_458 : X_OR2
    port map (
      I0 => dflag_OBUF_D2_PT_0,
      I1 => dflag_OBUF_D2_PT_1,
      O => dflag_OBUF_D2
    );
  dflag_OBUF_EXP_PT_0_459 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN7,
      I8 => Inst_fifo2_cnt_val(4),
      I9 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN9,
      I10 => Inst_fifo2_cnt_val(3),
      I11 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN11,
      I12 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN12,
      I13 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN13,
      I14 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN14,
      I15 => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN15,
      I16 => Inst_fifo2_cnt_val(0),
      I17 => Inst_fifo2_cnt_val(1),
      I18 => Inst_fifo2_cnt_val(2),
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => dflag_OBUF_EXP_PT_0
    );
  dflag_OBUF_EXP_PT_1_460 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN7,
      I8 => Inst_fifo2_cnt_val(4),
      I9 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN9,
      I10 => Inst_fifo2_cnt_val(3),
      I11 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN11,
      I12 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN12,
      I13 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN13,
      I14 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN14,
      I15 => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN15,
      I16 => Inst_fifo2_cnt_val(0),
      I17 => Inst_fifo2_cnt_val(1),
      I18 => Inst_fifo2_cnt_val(2),
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => dflag_OBUF_EXP_PT_1
    );
  dflag_OBUF_EXP_tsimrenamed_net_Q_461 : X_OR2
    port map (
      I0 => dflag_OBUF_EXP_PT_0,
      I1 => dflag_OBUF_EXP_PT_1,
      O => dflag_OBUF_EXP_tsimrenamed_net_Q
    );
  latchtrig_OBUF_462 : X_BUF
    port map (
      I => latchtrig_OBUF_Q,
      O => latchtrig_OBUF
    );
  latchtrig_OBUF_Q_463 : X_BUF
    port map (
      I => latchtrig_OBUF_D,
      O => latchtrig_OBUF_Q
    );
  latchtrig_OBUF_D_464 : X_XOR2
    port map (
      I0 => NlwInverterSignal_latchtrig_OBUF_D_IN0,
      I1 => latchtrig_OBUF_D2,
      O => latchtrig_OBUF_D
    );
  latchtrig_OBUF_D1_465 : X_ZERO
    port map (
      O => latchtrig_OBUF_D1
    );
  latchtrig_OBUF_D2_466 : X_AND4
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_latchtrig_OBUF_D2_IN3,
      O => latchtrig_OBUF_D2
    );
  ren1_OBUF_Q_467 : X_BUF
    port map (
      I => ren1_OBUF_Q_3,
      O => ren1_OBUF_Q
    );
  ren1_OBUF_Q_468 : X_BUF
    port map (
      I => ren1_OBUF_D,
      O => ren1_OBUF_Q_3
    );
  ren1_OBUF_D_469 : X_XOR2
    port map (
      I0 => NlwInverterSignal_ren1_OBUF_D_IN0,
      I1 => ren1_OBUF_D2,
      O => ren1_OBUF_D
    );
  ren1_OBUF_D1_470 : X_ZERO
    port map (
      O => ren1_OBUF_D1
    );
  ren1_OBUF_D2_471 : X_AND2
    port map (
      I0 => rst1_OBUF,
      I1 => Inst_fifo1_state_FFD2,
      O => ren1_OBUF_D2
    );
  ren2_OBUF_472 : X_BUF
    port map (
      I => ren2_OBUF_Q,
      O => ren2_OBUF
    );
  ren2_OBUF_Q_473 : X_BUF
    port map (
      I => ren2_OBUF_D,
      O => ren2_OBUF_Q
    );
  ren2_OBUF_D_474 : X_XOR2
    port map (
      I0 => NlwInverterSignal_ren2_OBUF_D_IN0,
      I1 => ren2_OBUF_D2,
      O => ren2_OBUF_D
    );
  ren2_OBUF_D1_475 : X_ZERO
    port map (
      O => ren2_OBUF_D1
    );
  ren2_OBUF_D2_PT_0_476 : X_AND4
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN3,
      O => ren2_OBUF_D2_PT_0
    );
  ren2_OBUF_D2_PT_1_477 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN3,
      I4 => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4,
      O => ren2_OBUF_D2_PT_1
    );
  ren2_OBUF_D2_PT_2_478 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN3,
      I4 => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4,
      O => ren2_OBUF_D2_PT_2
    );
  ren2_OBUF_D2_PT_3_479 : X_AND6
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN3,
      I4 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4,
      I5 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5,
      O => ren2_OBUF_D2_PT_3
    );
  ren2_OBUF_D2_PT_4_480 : X_AND6
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN3,
      I4 => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN4,
      I5 => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN5,
      O => ren2_OBUF_D2_PT_4
    );
  ren2_OBUF_D2_481 : X_OR5
    port map (
      I0 => ren2_OBUF_D2_PT_0,
      I1 => ren2_OBUF_D2_PT_1,
      I2 => ren2_OBUF_D2_PT_2,
      I3 => ren2_OBUF_D2_PT_3,
      I4 => ren2_OBUF_D2_PT_4,
      O => ren2_OBUF_D2
    );
  rst2_OBUF_482 : X_BUF
    port map (
      I => rst2_OBUF_Q,
      O => rst2_OBUF
    );
  rst2_OBUF_Q_483 : X_BUF
    port map (
      I => rst2_OBUF_D,
      O => rst2_OBUF_Q
    );
  rst2_OBUF_D_484 : X_XOR2
    port map (
      I0 => NlwInverterSignal_rst2_OBUF_D_IN0,
      I1 => rst2_OBUF_D2,
      O => rst2_OBUF_D
    );
  rst2_OBUF_D1_485 : X_ZERO
    port map (
      O => rst2_OBUF_D1
    );
  rst2_OBUF_D2_486 : X_AND3
    port map (
      I0 => NlwInverterSignal_rst2_OBUF_D2_IN0,
      I1 => NlwInverterSignal_rst2_OBUF_D2_IN1,
      I2 => NlwInverterSignal_rst2_OBUF_D2_IN2,
      O => rst2_OBUF_D2
    );
  rst3_OBUF_487 : X_BUF
    port map (
      I => rst3_OBUF_Q,
      O => rst3_OBUF
    );
  rst3_OBUF_Q_488 : X_BUF
    port map (
      I => rst3_OBUF_D,
      O => rst3_OBUF_Q
    );
  rst3_OBUF_D_489 : X_XOR2
    port map (
      I0 => NlwInverterSignal_rst3_OBUF_D_IN0,
      I1 => rst3_OBUF_D2,
      O => rst3_OBUF_D
    );
  rst3_OBUF_D1_490 : X_ZERO
    port map (
      O => rst3_OBUF_D1
    );
  rst3_OBUF_D2_491 : X_AND2
    port map (
      I0 => NlwInverterSignal_rst3_OBUF_D2_IN0,
      I1 => NlwInverterSignal_rst3_OBUF_D2_IN1,
      O => rst3_OBUF_D2
    );
  wen1_OBUF_Q_492 : X_BUF
    port map (
      I => wen1_OBUF_Q_4,
      O => wen1_OBUF_Q
    );
  wen1_OBUF_tsimcreated_prld_Q_493 : X_OR2
    port map (
      I0 => FSR_IO_2,
      I1 => PRLD,
      O => wen1_OBUF_tsimcreated_prld_Q
    );
  wen1_OBUF_REG : X_FF
    port map (
      I => wen1_OBUF_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => wen1_OBUF_tsimcreated_prld_Q,
      RST => Gnd,
      O => wen1_OBUF_Q_4
    );
  wen1_OBUF_D_494 : X_XOR2
    port map (
      I0 => NlwInverterSignal_wen1_OBUF_D_IN0,
      I1 => wen1_OBUF_D2,
      O => wen1_OBUF_D
    );
  wen1_OBUF_D1_495 : X_ZERO
    port map (
      O => wen1_OBUF_D1
    );
  wen1_OBUF_D2_PT_0_496 : X_AND3
    port map (
      I0 => rst1_OBUF,
      I1 => NlwInverterSignal_wen1_OBUF_D2_PT_0_IN1,
      I2 => full3_IBUF,
      O => wen1_OBUF_D2_PT_0
    );
  wen1_OBUF_D2_PT_1_497 : X_AND3
    port map (
      I0 => NlwInverterSignal_wen1_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_wen1_OBUF_D2_PT_1_IN1,
      I2 => full3_IBUF,
      O => wen1_OBUF_D2_PT_1
    );
  wen1_OBUF_D2_498 : X_OR2
    port map (
      I0 => wen1_OBUF_D2_PT_0,
      I1 => wen1_OBUF_D2_PT_1,
      O => wen1_OBUF_D2
    );
  wen2_OBUF_Q_499 : X_BUF
    port map (
      I => wen2_OBUF_Q_5,
      O => wen2_OBUF_Q
    );
  wen2_OBUF_EXP_500 : X_BUF
    port map (
      I => wen2_OBUF_EXP_tsimrenamed_net_Q,
      O => wen2_OBUF_EXP
    );
  wen2_OBUF_Q_501 : X_BUF
    port map (
      I => wen2_OBUF_D,
      O => wen2_OBUF_Q_5
    );
  wen2_OBUF_D_502 : X_XOR2
    port map (
      I0 => NlwInverterSignal_wen2_OBUF_D_IN0,
      I1 => wen2_OBUF_D2,
      O => wen2_OBUF_D
    );
  wen2_OBUF_D1_503 : X_ZERO
    port map (
      O => wen2_OBUF_D1
    );
  wen2_OBUF_D2_PT_0_504 : X_AND2
    port map (
      I0 => wen3_OBUF_EXP,
      I1 => wen3_OBUF_EXP,
      O => wen2_OBUF_D2_PT_0
    );
  wen2_OBUF_D2_PT_1_505 : X_AND4
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3,
      O => wen2_OBUF_D2_PT_1
    );
  wen2_OBUF_D2_PT_2_506 : X_AND4
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      O => wen2_OBUF_D2_PT_2
    );
  wen2_OBUF_D2_PT_3_507 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3,
      I4 => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4,
      O => wen2_OBUF_D2_PT_3
    );
  wen2_OBUF_D2_508 : X_OR4
    port map (
      I0 => wen2_OBUF_D2_PT_0,
      I1 => wen2_OBUF_D2_PT_1,
      I2 => wen2_OBUF_D2_PT_2,
      I3 => wen2_OBUF_D2_PT_3,
      O => wen2_OBUF_D2
    );
  wen2_OBUF_EXP_PT_0_509 : X_AND4
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => NlwInverterSignal_wen2_OBUF_EXP_PT_0_IN1,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I3 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => wen2_OBUF_EXP_PT_0
    );
  wen2_OBUF_EXP_PT_1_510 : X_AND4
    port map (
      I0 => Inst_fifo2_state_FFT1,
      I1 => Inst_fifo2_state_FFT3,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I3 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => wen2_OBUF_EXP_PT_1
    );
  wen2_OBUF_EXP_tsimrenamed_net_Q_511 : X_OR2
    port map (
      I0 => wen2_OBUF_EXP_PT_0,
      I1 => wen2_OBUF_EXP_PT_1,
      O => wen2_OBUF_EXP_tsimrenamed_net_Q
    );
  wen3_OBUF_512 : X_BUF
    port map (
      I => wen3_OBUF_Q,
      O => wen3_OBUF
    );
  wen3_OBUF_EXP_513 : X_BUF
    port map (
      I => wen3_OBUF_EXP_tsimrenamed_net_Q,
      O => wen3_OBUF_EXP
    );
  wen3_OBUF_Q_514 : X_BUF
    port map (
      I => wen3_OBUF_D,
      O => wen3_OBUF_Q
    );
  wen3_OBUF_D_515 : X_XOR2
    port map (
      I0 => NlwInverterSignal_wen3_OBUF_D_IN0,
      I1 => wen3_OBUF_D2,
      O => wen3_OBUF_D
    );
  wen3_OBUF_D1_516 : X_ZERO
    port map (
      O => wen3_OBUF_D1
    );
  wen3_OBUF_D2_517 : X_AND2
    port map (
      I0 => Inst_fifo3_state_FFD2,
      I1 => Inst_fifo3_state_FFD1,
      O => wen3_OBUF_D2
    );
  wen3_OBUF_EXP_PT_0_518 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN4,
      O => wen3_OBUF_EXP_PT_0
    );
  wen3_OBUF_EXP_PT_1_519 : X_AND6
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN5,
      O => wen3_OBUF_EXP_PT_1
    );
  wen3_OBUF_EXP_PT_2_520 : X_AND6
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT3,
      I3 => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN5,
      O => wen3_OBUF_EXP_PT_2
    );
  wen3_OBUF_EXP_tsimrenamed_net_Q_521 : X_OR3
    port map (
      I0 => wen3_OBUF_EXP_PT_0,
      I1 => wen3_OBUF_EXP_PT_1,
      I2 => wen3_OBUF_EXP_PT_2,
      O => wen3_OBUF_EXP_tsimrenamed_net_Q
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_UIM_522 : X_BUF
    port map (
      I => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_Q,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_UIM
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_Q_523 : X_BUF
    port map (
      I => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_Q
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D_524 : X_XOR2
    port map (
      I0 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D1,
      I1 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D1_525 : X_ZERO
    port map (
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D1
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_0_526 : X_AND2
    port map (
      I0 => EXP10_EXP,
      I1 => EXP10_EXP,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_0
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_1_527 : X_AND2
    port map (
      I0 => EXP11_EXP,
      I1 => EXP11_EXP,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_1
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_528 : X_AND16
    port map (
      I0 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN2,
      I3 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN3,
      I4 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN4,
      I5 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN5,
      I6 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN6,
      I7 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN7,
      I8 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_529 : X_AND16
    port map (
      I0 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN0,
      I1 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN1,
      I2 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN2,
      I3 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN3,
      I4 => Inst_fifo2_cnt_val(5),
      I5 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN5,
      I6 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN6,
      I7 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN7,
      I8 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_530 : X_AND16
    port map (
      I0 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN2,
      I3 => Inst_fifo2_cnt_val(3),
      I4 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN4,
      I5 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN5,
      I6 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN6,
      I7 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN7,
      I8 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN8,
      I9 => Inst_fifo2_cnt_val(0),
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_531 : X_AND16
    port map (
      I0 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN2,
      I3 => Inst_fifo2_cnt_val(3),
      I4 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN4,
      I5 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN5,
      I6 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN6,
      I7 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN7,
      I8 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN8,
      I9 => Inst_fifo2_cnt_val(1),
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_532 : X_AND16
    port map (
      I0 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN2,
      I3 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN3,
      I4 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN4,
      I5 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN5,
      I6 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN6,
      I7 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN7,
      I8 => Inst_fifo2_cnt_val(2),
      I9 => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6
    );
  Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_533 : X_OR7
    port map (
      I0 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_0,
      I1 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_1,
      I2 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2,
      I3 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3,
      I4 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4,
      I5 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5,
      I6 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6,
      O => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2
    );
  trigger_out_trigger_out_RSTF_INT_UIM_534 : X_BUF
    port map (
      I => trigger_out_trigger_out_RSTF_INT_Q,
      O => trigger_out_trigger_out_RSTF_INT_UIM
    );
  trigger_out_trigger_out_RSTF_INT_Q_535 : X_BUF
    port map (
      I => trigger_out_trigger_out_RSTF_INT_D,
      O => trigger_out_trigger_out_RSTF_INT_Q
    );
  trigger_out_trigger_out_RSTF_INT_D_536 : X_XOR2
    port map (
      I0 => trigger_out_trigger_out_RSTF_INT_D1,
      I1 => trigger_out_trigger_out_RSTF_INT_D2,
      O => trigger_out_trigger_out_RSTF_INT_D
    );
  trigger_out_trigger_out_RSTF_INT_D1_537 : X_ZERO
    port map (
      O => trigger_out_trigger_out_RSTF_INT_D1
    );
  trigger_out_trigger_out_RSTF_INT_D2_538 : X_AND2
    port map (
      I0 => reset_IBUF,
      I1 => rstdataready_IBUF,
      O => trigger_out_trigger_out_RSTF_INT_D2
    );
  EXP10_EXP_539 : X_BUF
    port map (
      I => EXP10_EXP_tsimrenamed_net_Q,
      O => EXP10_EXP
    );
  EXP10_EXP_PT_0_540 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP10_EXP_PT_0_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_EXP10_EXP_PT_0_IN2,
      I3 => Inst_fifo2_cnt_val(3),
      I4 => NlwInverterSignal_EXP10_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP10_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_EXP10_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_EXP10_EXP_PT_0_IN7,
      I8 => NlwInverterSignal_EXP10_EXP_PT_0_IN8,
      I9 => Inst_fifo2_cnt_val(2),
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP10_EXP_PT_0
    );
  EXP10_EXP_PT_1_541 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP10_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP10_EXP_PT_1_IN1,
      I2 => Inst_fifo2_cnt_val(3),
      I3 => NlwInverterSignal_EXP10_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP10_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP10_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP10_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_EXP10_EXP_PT_1_IN7,
      I8 => Inst_fifo2_cnt_val(1),
      I9 => NlwInverterSignal_EXP10_EXP_PT_1_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP10_EXP_PT_1
    );
  EXP10_EXP_tsimrenamed_net_Q_542 : X_OR2
    port map (
      I0 => EXP10_EXP_PT_0,
      I1 => EXP10_EXP_PT_1,
      O => EXP10_EXP_tsimrenamed_net_Q
    );
  EXP11_EXP_543 : X_BUF
    port map (
      I => EXP11_EXP_tsimrenamed_net_Q,
      O => EXP11_EXP
    );
  EXP11_EXP_PT_0_544 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP11_EXP_PT_0_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      I2 => NlwInverterSignal_EXP11_EXP_PT_0_IN2,
      I3 => Inst_fifo2_cnt_val(3),
      I4 => NlwInverterSignal_EXP11_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP11_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_EXP11_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_EXP11_EXP_PT_0_IN7,
      I8 => NlwInverterSignal_EXP11_EXP_PT_0_IN8,
      I9 => NlwInverterSignal_EXP11_EXP_PT_0_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP11_EXP_PT_0
    );
  EXP11_EXP_PT_1_545 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP11_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP11_EXP_PT_1_IN1,
      I2 => Inst_fifo2_cnt_val(3),
      I3 => NlwInverterSignal_EXP11_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP11_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP11_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP11_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_EXP11_EXP_PT_1_IN7,
      I8 => Inst_fifo2_cnt_val(2),
      I9 => NlwInverterSignal_EXP11_EXP_PT_1_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP11_EXP_PT_1
    );
  EXP11_EXP_PT_2_546 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP11_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP11_EXP_PT_2_IN1,
      I2 => Inst_fifo2_cnt_val(3),
      I3 => NlwInverterSignal_EXP11_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_EXP11_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP11_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_EXP11_EXP_PT_2_IN6,
      I7 => NlwInverterSignal_EXP11_EXP_PT_2_IN7,
      I8 => NlwInverterSignal_EXP11_EXP_PT_2_IN8,
      I9 => NlwInverterSignal_EXP11_EXP_PT_2_IN9,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP11_EXP_PT_2
    );
  EXP11_EXP_PT_3_547 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP11_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP11_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_EXP11_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_EXP11_EXP_PT_3_IN3,
      I4 => NlwInverterSignal_EXP11_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP11_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_EXP11_EXP_PT_3_IN6,
      I7 => Inst_fifo2_cnt_val(0),
      I8 => Inst_fifo2_cnt_val(2),
      I9 => NlwInverterSignal_EXP11_EXP_PT_3_IN9,
      I10 => NlwInverterSignal_EXP11_EXP_PT_3_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP11_EXP_PT_3
    );
  EXP11_EXP_PT_4_548 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP11_EXP_PT_4_IN0,
      I1 => NlwInverterSignal_EXP11_EXP_PT_4_IN1,
      I2 => NlwInverterSignal_EXP11_EXP_PT_4_IN2,
      I3 => NlwInverterSignal_EXP11_EXP_PT_4_IN3,
      I4 => NlwInverterSignal_EXP11_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP11_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_EXP11_EXP_PT_4_IN6,
      I7 => Inst_fifo2_cnt_val(1),
      I8 => Inst_fifo2_cnt_val(2),
      I9 => NlwInverterSignal_EXP11_EXP_PT_4_IN9,
      I10 => NlwInverterSignal_EXP11_EXP_PT_4_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP11_EXP_PT_4
    );
  EXP11_EXP_tsimrenamed_net_Q_549 : X_OR5
    port map (
      I0 => EXP11_EXP_PT_0,
      I1 => EXP11_EXP_PT_1,
      I2 => EXP11_EXP_PT_2,
      I3 => EXP11_EXP_PT_3,
      I4 => EXP11_EXP_PT_4,
      O => EXP11_EXP_tsimrenamed_net_Q
    );
  EXP12_EXP_550 : X_BUF
    port map (
      I => EXP12_EXP_tsimrenamed_net_Q,
      O => EXP12_EXP
    );
  EXP12_EXP_PT_0_551 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP12_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP12_EXP_PT_0_IN1,
      O => EXP12_EXP_PT_0
    );
  EXP12_EXP_PT_1_552 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP12_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP12_EXP_PT_1_IN1,
      O => EXP12_EXP_PT_1
    );
  EXP12_EXP_PT_2_553 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(9),
      I1 => NlwInverterSignal_EXP12_EXP_PT_2_IN1,
      O => EXP12_EXP_PT_2
    );
  EXP12_EXP_PT_3_554 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(7),
      I1 => NlwInverterSignal_EXP12_EXP_PT_3_IN1,
      O => EXP12_EXP_PT_3
    );
  EXP12_EXP_PT_4_555 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(8),
      I1 => NlwInverterSignal_EXP12_EXP_PT_4_IN1,
      O => EXP12_EXP_PT_4
    );
  EXP12_EXP_tsimrenamed_net_Q_556 : X_OR5
    port map (
      I0 => EXP12_EXP_PT_0,
      I1 => EXP12_EXP_PT_1,
      I2 => EXP12_EXP_PT_2,
      I3 => EXP12_EXP_PT_3,
      I4 => EXP12_EXP_PT_4,
      O => EXP12_EXP_tsimrenamed_net_Q
    );
  EXP13_EXP_557 : X_BUF
    port map (
      I => EXP13_EXP_tsimrenamed_net_Q,
      O => EXP13_EXP
    );
  EXP13_EXP_PT_0_558 : X_AND2
    port map (
      I0 => EXP14_EXP,
      I1 => EXP14_EXP,
      O => EXP13_EXP_PT_0
    );
  EXP13_EXP_PT_1_559 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP13_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP13_EXP_PT_1_IN1,
      O => EXP13_EXP_PT_1
    );
  EXP13_EXP_PT_2_560 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP13_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => EXP13_EXP_PT_2
    );
  EXP13_EXP_PT_3_561 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP13_EXP_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => EXP13_EXP_PT_3
    );
  EXP13_EXP_PT_4_562 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(4),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP13_EXP_PT_4_IN2,
      O => EXP13_EXP_PT_4
    );
  EXP13_EXP_PT_5_563 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(3),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP13_EXP_PT_5_IN2,
      O => EXP13_EXP_PT_5
    );
  EXP13_EXP_tsimrenamed_net_Q_564 : X_OR6
    port map (
      I0 => EXP13_EXP_PT_0,
      I1 => EXP13_EXP_PT_1,
      I2 => EXP13_EXP_PT_2,
      I3 => EXP13_EXP_PT_3,
      I4 => EXP13_EXP_PT_4,
      I5 => EXP13_EXP_PT_5,
      O => EXP13_EXP_tsimrenamed_net_Q
    );
  EXP14_EXP_565 : X_BUF
    port map (
      I => EXP14_EXP_tsimrenamed_net_Q,
      O => EXP14_EXP
    );
  EXP14_EXP_PT_0_566 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => EXP14_EXP_PT_0
    );
  EXP14_EXP_PT_1_567 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP14_EXP_PT_1_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => EXP14_EXP_PT_1
    );
  EXP14_EXP_PT_2_568 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP14_EXP_PT_2_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => EXP14_EXP_PT_2
    );
  EXP14_EXP_tsimrenamed_net_Q_569 : X_OR3
    port map (
      I0 => EXP14_EXP_PT_0,
      I1 => EXP14_EXP_PT_1,
      I2 => EXP14_EXP_PT_2,
      O => EXP14_EXP_tsimrenamed_net_Q
    );
  EXP15_EXP_570 : X_BUF
    port map (
      I => EXP15_EXP_tsimrenamed_net_Q,
      O => EXP15_EXP
    );
  EXP15_EXP_PT_0_571 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => EXP15_EXP_PT_0
    );
  EXP15_EXP_PT_1_572 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP15_EXP_PT_1_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => EXP15_EXP_PT_1
    );
  EXP15_EXP_PT_2_573 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP15_EXP_PT_2_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => EXP15_EXP_PT_2
    );
  EXP15_EXP_PT_3_574 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP15_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP15_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_EXP15_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_EXP15_EXP_PT_3_IN3,
      I4 => NlwInverterSignal_EXP15_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP15_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_EXP15_EXP_PT_3_IN6,
      I7 => NlwInverterSignal_EXP15_EXP_PT_3_IN7,
      O => EXP15_EXP_PT_3
    );
  EXP15_EXP_PT_4_575 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP15_EXP_PT_4_IN0,
      I1 => NlwInverterSignal_EXP15_EXP_PT_4_IN1,
      I2 => NlwInverterSignal_EXP15_EXP_PT_4_IN2,
      I3 => NlwInverterSignal_EXP15_EXP_PT_4_IN3,
      I4 => NlwInverterSignal_EXP15_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP15_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_EXP15_EXP_PT_4_IN6,
      I7 => NlwInverterSignal_EXP15_EXP_PT_4_IN7,
      I8 => NlwInverterSignal_EXP15_EXP_PT_4_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP15_EXP_PT_4
    );
  EXP15_EXP_tsimrenamed_net_Q_576 : X_OR5
    port map (
      I0 => EXP15_EXP_PT_0,
      I1 => EXP15_EXP_PT_1,
      I2 => EXP15_EXP_PT_2,
      I3 => EXP15_EXP_PT_3,
      I4 => EXP15_EXP_PT_4,
      O => EXP15_EXP_tsimrenamed_net_Q
    );
  EXP16_EXP_577 : X_BUF
    port map (
      I => EXP16_EXP_tsimrenamed_net_Q,
      O => EXP16_EXP
    );
  EXP16_EXP_PT_0_578 : X_AND2
    port map (
      I0 => EXP15_EXP,
      I1 => EXP15_EXP,
      O => EXP16_EXP_PT_0
    );
  EXP16_EXP_PT_1_579 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP16_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP16_EXP_PT_1_IN1,
      O => EXP16_EXP_PT_1
    );
  EXP16_EXP_PT_2_580 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP16_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP16_EXP_PT_2_IN1,
      O => EXP16_EXP_PT_2
    );
  EXP16_EXP_PT_3_581 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(9),
      I1 => NlwInverterSignal_EXP16_EXP_PT_3_IN1,
      O => EXP16_EXP_PT_3
    );
  EXP16_EXP_PT_4_582 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(7),
      I1 => NlwInverterSignal_EXP16_EXP_PT_4_IN1,
      O => EXP16_EXP_PT_4
    );
  EXP16_EXP_PT_5_583 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(8),
      I1 => NlwInverterSignal_EXP16_EXP_PT_5_IN1,
      O => EXP16_EXP_PT_5
    );
  EXP16_EXP_tsimrenamed_net_Q_584 : X_OR6
    port map (
      I0 => EXP16_EXP_PT_0,
      I1 => EXP16_EXP_PT_1,
      I2 => EXP16_EXP_PT_2,
      I3 => EXP16_EXP_PT_3,
      I4 => EXP16_EXP_PT_4,
      I5 => EXP16_EXP_PT_5,
      O => EXP16_EXP_tsimrenamed_net_Q
    );
  EXP17_EXP_585 : X_BUF
    port map (
      I => EXP17_EXP_tsimrenamed_net_Q,
      O => EXP17_EXP
    );
  EXP17_EXP_PT_0_586 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP17_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP17_EXP_PT_0_IN1,
      O => EXP17_EXP_PT_0
    );
  EXP17_EXP_PT_1_587 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP17_EXP_PT_1_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => EXP17_EXP_PT_1
    );
  EXP17_EXP_PT_2_588 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP17_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => EXP17_EXP_PT_2
    );
  EXP17_EXP_PT_3_589 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(4),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP17_EXP_PT_3_IN2,
      O => EXP17_EXP_PT_3
    );
  EXP17_EXP_PT_4_590 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(3),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP17_EXP_PT_4_IN2,
      O => EXP17_EXP_PT_4
    );
  EXP17_EXP_tsimrenamed_net_Q_591 : X_OR5
    port map (
      I0 => EXP17_EXP_PT_0,
      I1 => EXP17_EXP_PT_1,
      I2 => EXP17_EXP_PT_2,
      I3 => EXP17_EXP_PT_3,
      I4 => EXP17_EXP_PT_4,
      O => EXP17_EXP_tsimrenamed_net_Q
    );
  EXP18_EXP_592 : X_BUF
    port map (
      I => EXP18_EXP_tsimrenamed_net_Q,
      O => EXP18_EXP
    );
  EXP18_EXP_PT_0_593 : X_AND2
    port map (
      I0 => Inst_fifo3_cnt_7_EXP,
      I1 => Inst_fifo3_cnt_7_EXP,
      O => EXP18_EXP_PT_0
    );
  EXP18_EXP_PT_1_594 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(10),
      I1 => NlwInverterSignal_EXP18_EXP_PT_1_IN1,
      O => EXP18_EXP_PT_1
    );
  EXP18_EXP_PT_2_595 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(6),
      I1 => NlwInverterSignal_EXP18_EXP_PT_2_IN1,
      O => EXP18_EXP_PT_2
    );
  EXP18_EXP_PT_3_596 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(7),
      I1 => NlwInverterSignal_EXP18_EXP_PT_3_IN1,
      O => EXP18_EXP_PT_3
    );
  EXP18_EXP_PT_4_597 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(8),
      I1 => NlwInverterSignal_EXP18_EXP_PT_4_IN1,
      O => EXP18_EXP_PT_4
    );
  EXP18_EXP_PT_5_598 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(11),
      I1 => NlwInverterSignal_EXP18_EXP_PT_5_IN1,
      O => EXP18_EXP_PT_5
    );
  EXP18_EXP_tsimrenamed_net_Q_599 : X_OR6
    port map (
      I0 => EXP18_EXP_PT_0,
      I1 => EXP18_EXP_PT_1,
      I2 => EXP18_EXP_PT_2,
      I3 => EXP18_EXP_PT_3,
      I4 => EXP18_EXP_PT_4,
      I5 => EXP18_EXP_PT_5,
      O => EXP18_EXP_tsimrenamed_net_Q
    );
  EXP19_EXP_600 : X_BUF
    port map (
      I => EXP19_EXP_tsimrenamed_net_Q,
      O => EXP19_EXP
    );
  EXP19_EXP_PT_0_601 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val_9_EXP,
      I1 => Inst_fifo2_cnt_val_9_EXP,
      O => EXP19_EXP_PT_0
    );
  EXP19_EXP_PT_1_602 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_EXP19_EXP_PT_1_IN3,
      I4 => Inst_fifo2_cnt_val(8),
      O => EXP19_EXP_PT_1
    );
  EXP19_EXP_PT_2_603 : X_AND5
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_EXP19_EXP_PT_2_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => Inst_fifo2_cnt_val(8),
      O => EXP19_EXP_PT_2
    );
  EXP19_EXP_PT_3_604 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP19_EXP_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP19_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP19_EXP_PT_3_IN5,
      I6 => Inst_fifo2_cnt_val(8),
      O => EXP19_EXP_PT_3
    );
  EXP19_EXP_PT_4_605 : X_AND7
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP19_EXP_PT_4_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP19_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP19_EXP_PT_4_IN5,
      I6 => Inst_fifo2_cnt_val(8),
      O => EXP19_EXP_PT_4
    );
  EXP19_EXP_PT_5_606 : X_AND8
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP19_EXP_PT_5_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP19_EXP_PT_5_IN4,
      I5 => NlwInverterSignal_EXP19_EXP_PT_5_IN5,
      I6 => NlwInverterSignal_EXP19_EXP_PT_5_IN6,
      I7 => Inst_fifo2_cnt_val(8),
      O => EXP19_EXP_PT_5
    );
  EXP19_EXP_tsimrenamed_net_Q_607 : X_OR6
    port map (
      I0 => EXP19_EXP_PT_0,
      I1 => EXP19_EXP_PT_1,
      I2 => EXP19_EXP_PT_2,
      I3 => EXP19_EXP_PT_3,
      I4 => EXP19_EXP_PT_4,
      I5 => EXP19_EXP_PT_5,
      O => EXP19_EXP_tsimrenamed_net_Q
    );
  EXP20_EXP_608 : X_BUF
    port map (
      I => EXP20_EXP_tsimrenamed_net_Q,
      O => EXP20_EXP
    );
  EXP20_EXP_tsimrenamed_net_Q_609 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0,
      I1 => Inst_fifo2_state_FFT1,
      I2 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2,
      I3 => rst1_OBUF,
      I4 => Inst_fifo1_state_FFD2,
      I5 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5,
      I6 => full3_IBUF,
      O => EXP20_EXP_tsimrenamed_net_Q
    );
  EXP21_EXP_610 : X_BUF
    port map (
      I => EXP21_EXP_tsimrenamed_net_Q,
      O => EXP21_EXP
    );
  EXP21_EXP_PT_0_611 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP21_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP21_EXP_PT_0_IN1,
      I2 => NlwInverterSignal_EXP21_EXP_PT_0_IN2,
      I3 => NlwInverterSignal_EXP21_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_EXP21_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP21_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_EXP21_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_EXP21_EXP_PT_0_IN7,
      O => EXP21_EXP_PT_0
    );
  EXP21_EXP_PT_1_612 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP21_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP21_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_EXP21_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_EXP21_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP21_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP21_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP21_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_EXP21_EXP_PT_1_IN7,
      O => EXP21_EXP_PT_1
    );
  EXP21_EXP_PT_2_613 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP21_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP21_EXP_PT_2_IN1,
      I2 => NlwInverterSignal_EXP21_EXP_PT_2_IN2,
      I3 => NlwInverterSignal_EXP21_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_EXP21_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP21_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_EXP21_EXP_PT_2_IN6,
      I7 => NlwInverterSignal_EXP21_EXP_PT_2_IN7,
      O => EXP21_EXP_PT_2
    );
  EXP21_EXP_tsimrenamed_net_Q_614 : X_OR3
    port map (
      I0 => EXP21_EXP_PT_0,
      I1 => EXP21_EXP_PT_1,
      I2 => EXP21_EXP_PT_2,
      O => EXP21_EXP_tsimrenamed_net_Q
    );
  EXP22_EXP_615 : X_BUF
    port map (
      I => EXP22_EXP_tsimrenamed_net_Q,
      O => EXP22_EXP
    );
  EXP22_EXP_PT_0_616 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_0_IN0,
      I1 => Inst_fifo2_cnt_val(5),
      O => EXP22_EXP_PT_0
    );
  EXP22_EXP_PT_1_617 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP22_EXP_PT_1_IN1,
      I2 => Inst_fifo2_cnt_val(5),
      O => EXP22_EXP_PT_1
    );
  EXP22_EXP_PT_2_618 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP22_EXP_PT_2_IN1,
      I2 => Inst_fifo2_cnt_val(5),
      O => EXP22_EXP_PT_2
    );
  EXP22_EXP_PT_3_619 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP22_EXP_PT_3_IN1,
      I2 => Inst_fifo2_cnt_val(5),
      O => EXP22_EXP_PT_3
    );
  EXP22_EXP_PT_4_620 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_4_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      I3 => Inst_fifo2_cnt_val(5),
      O => EXP22_EXP_PT_4
    );
  EXP22_EXP_tsimrenamed_net_Q_621 : X_OR5
    port map (
      I0 => EXP22_EXP_PT_0,
      I1 => EXP22_EXP_PT_1,
      I2 => EXP22_EXP_PT_2,
      I3 => EXP22_EXP_PT_3,
      I4 => EXP22_EXP_PT_4,
      O => EXP22_EXP_tsimrenamed_net_Q
    );
  EXP23_EXP_622 : X_BUF
    port map (
      I => EXP23_EXP_tsimrenamed_net_Q,
      O => EXP23_EXP
    );
  EXP23_EXP_PT_0_623 : X_AND2
    port map (
      I0 => dflag_OBUF_EXP,
      I1 => dflag_OBUF_EXP,
      O => EXP23_EXP_PT_0
    );
  EXP23_EXP_PT_1_624 : X_AND4
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => Inst_fifo2_cnt_val(5),
      O => EXP23_EXP_PT_1
    );
  EXP23_EXP_PT_2_625 : X_AND16
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_EXP23_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_EXP23_EXP_PT_2_IN4,
      I5 => Inst_fifo2_cnt_val(4),
      I6 => NlwInverterSignal_EXP23_EXP_PT_2_IN6,
      I7 => Inst_fifo2_cnt_val(3),
      I8 => NlwInverterSignal_EXP23_EXP_PT_2_IN8,
      I9 => NlwInverterSignal_EXP23_EXP_PT_2_IN9,
      I10 => NlwInverterSignal_EXP23_EXP_PT_2_IN10,
      I11 => NlwInverterSignal_EXP23_EXP_PT_2_IN11,
      I12 => NlwInverterSignal_EXP23_EXP_PT_2_IN12,
      I13 => Inst_fifo2_cnt_val(0),
      I14 => Inst_fifo2_cnt_val(1),
      I15 => Inst_fifo2_cnt_val(2),
      O => EXP23_EXP_PT_2
    );
  EXP23_EXP_PT_3_626 : X_AND16
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_EXP23_EXP_PT_3_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP23_EXP_PT_3_IN4,
      I5 => Inst_fifo2_cnt_val(4),
      I6 => NlwInverterSignal_EXP23_EXP_PT_3_IN6,
      I7 => Inst_fifo2_cnt_val(3),
      I8 => NlwInverterSignal_EXP23_EXP_PT_3_IN8,
      I9 => NlwInverterSignal_EXP23_EXP_PT_3_IN9,
      I10 => NlwInverterSignal_EXP23_EXP_PT_3_IN10,
      I11 => NlwInverterSignal_EXP23_EXP_PT_3_IN11,
      I12 => NlwInverterSignal_EXP23_EXP_PT_3_IN12,
      I13 => Inst_fifo2_cnt_val(0),
      I14 => Inst_fifo2_cnt_val(1),
      I15 => Inst_fifo2_cnt_val(2),
      O => EXP23_EXP_PT_3
    );
  EXP23_EXP_PT_4_627 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP23_EXP_PT_4_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP23_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP23_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_EXP23_EXP_PT_4_IN6,
      I7 => Inst_fifo2_cnt_val(4),
      I8 => NlwInverterSignal_EXP23_EXP_PT_4_IN8,
      I9 => Inst_fifo2_cnt_val(3),
      I10 => NlwInverterSignal_EXP23_EXP_PT_4_IN10,
      I11 => NlwInverterSignal_EXP23_EXP_PT_4_IN11,
      I12 => NlwInverterSignal_EXP23_EXP_PT_4_IN12,
      I13 => NlwInverterSignal_EXP23_EXP_PT_4_IN13,
      I14 => NlwInverterSignal_EXP23_EXP_PT_4_IN14,
      I15 => Inst_fifo2_cnt_val(0),
      I16 => Inst_fifo2_cnt_val(1),
      I17 => Inst_fifo2_cnt_val(2),
      I18 => Vcc,
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP23_EXP_PT_4
    );
  EXP23_EXP_PT_5_628 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP23_EXP_PT_5_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP23_EXP_PT_5_IN4,
      I5 => NlwInverterSignal_EXP23_EXP_PT_5_IN5,
      I6 => NlwInverterSignal_EXP23_EXP_PT_5_IN6,
      I7 => Inst_fifo2_cnt_val(4),
      I8 => NlwInverterSignal_EXP23_EXP_PT_5_IN8,
      I9 => Inst_fifo2_cnt_val(3),
      I10 => NlwInverterSignal_EXP23_EXP_PT_5_IN10,
      I11 => NlwInverterSignal_EXP23_EXP_PT_5_IN11,
      I12 => NlwInverterSignal_EXP23_EXP_PT_5_IN12,
      I13 => NlwInverterSignal_EXP23_EXP_PT_5_IN13,
      I14 => NlwInverterSignal_EXP23_EXP_PT_5_IN14,
      I15 => Inst_fifo2_cnt_val(0),
      I16 => Inst_fifo2_cnt_val(1),
      I17 => Inst_fifo2_cnt_val(2),
      I18 => Vcc,
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP23_EXP_PT_5
    );
  EXP23_EXP_tsimrenamed_net_Q_629 : X_OR6
    port map (
      I0 => EXP23_EXP_PT_0,
      I1 => EXP23_EXP_PT_1,
      I2 => EXP23_EXP_PT_2,
      I3 => EXP23_EXP_PT_3,
      I4 => EXP23_EXP_PT_4,
      I5 => EXP23_EXP_PT_5,
      O => EXP23_EXP_tsimrenamed_net_Q
    );
  EXP24_EXP_630 : X_BUF
    port map (
      I => EXP24_EXP_tsimrenamed_net_Q,
      O => EXP24_EXP
    );
  EXP24_EXP_PT_0_631 : X_AND16
    port map (
      I0 => reset_IBUF,
      I1 => NlwInverterSignal_EXP24_EXP_PT_0_IN1,
      I2 => Inst_fifo2_state_FFT1,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP24_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_EXP24_EXP_PT_0_IN6,
      I7 => Inst_fifo2_cnt_val(3),
      I8 => NlwInverterSignal_EXP24_EXP_PT_0_IN8,
      I9 => NlwInverterSignal_EXP24_EXP_PT_0_IN9,
      I10 => NlwInverterSignal_EXP24_EXP_PT_0_IN10,
      I11 => NlwInverterSignal_EXP24_EXP_PT_0_IN11,
      I12 => NlwInverterSignal_EXP24_EXP_PT_0_IN12,
      I13 => Inst_fifo2_cnt_val(0),
      I14 => Inst_fifo2_cnt_val(1),
      I15 => Inst_fifo2_cnt_val(2),
      O => EXP24_EXP_PT_0
    );
  EXP24_EXP_PT_1_632 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP24_EXP_PT_1_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP24_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP24_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_EXP24_EXP_PT_1_IN7,
      I8 => NlwInverterSignal_EXP24_EXP_PT_1_IN8,
      I9 => Inst_fifo2_cnt_val(3),
      I10 => NlwInverterSignal_EXP24_EXP_PT_1_IN10,
      I11 => NlwInverterSignal_EXP24_EXP_PT_1_IN11,
      I12 => NlwInverterSignal_EXP24_EXP_PT_1_IN12,
      I13 => NlwInverterSignal_EXP24_EXP_PT_1_IN13,
      I14 => NlwInverterSignal_EXP24_EXP_PT_1_IN14,
      I15 => Inst_fifo2_cnt_val(0),
      I16 => Inst_fifo2_cnt_val(1),
      I17 => Inst_fifo2_cnt_val(2),
      I18 => Vcc,
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP24_EXP_PT_1
    );
  EXP24_EXP_PT_2_633 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP24_EXP_PT_2_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP24_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_EXP24_EXP_PT_2_IN6,
      I7 => NlwInverterSignal_EXP24_EXP_PT_2_IN7,
      I8 => NlwInverterSignal_EXP24_EXP_PT_2_IN8,
      I9 => Inst_fifo2_cnt_val(3),
      I10 => NlwInverterSignal_EXP24_EXP_PT_2_IN10,
      I11 => NlwInverterSignal_EXP24_EXP_PT_2_IN11,
      I12 => NlwInverterSignal_EXP24_EXP_PT_2_IN12,
      I13 => NlwInverterSignal_EXP24_EXP_PT_2_IN13,
      I14 => NlwInverterSignal_EXP24_EXP_PT_2_IN14,
      I15 => Inst_fifo2_cnt_val(0),
      I16 => Inst_fifo2_cnt_val(1),
      I17 => Inst_fifo2_cnt_val(2),
      I18 => Vcc,
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP24_EXP_PT_2
    );
  EXP24_EXP_PT_3_634 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP24_EXP_PT_3_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP24_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_EXP24_EXP_PT_3_IN6,
      I7 => NlwInverterSignal_EXP24_EXP_PT_3_IN7,
      I8 => NlwInverterSignal_EXP24_EXP_PT_3_IN8,
      I9 => NlwInverterSignal_EXP24_EXP_PT_3_IN9,
      I10 => Inst_fifo2_cnt_val(3),
      I11 => NlwInverterSignal_EXP24_EXP_PT_3_IN11,
      I12 => NlwInverterSignal_EXP24_EXP_PT_3_IN12,
      I13 => NlwInverterSignal_EXP24_EXP_PT_3_IN13,
      I14 => NlwInverterSignal_EXP24_EXP_PT_3_IN14,
      I15 => NlwInverterSignal_EXP24_EXP_PT_3_IN15,
      I16 => Inst_fifo2_cnt_val(0),
      I17 => Inst_fifo2_cnt_val(1),
      I18 => Inst_fifo2_cnt_val(2),
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP24_EXP_PT_3
    );
  EXP24_EXP_PT_4_635 : X_AND32
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => NlwInverterSignal_EXP24_EXP_PT_4_IN2,
      I3 => Inst_fifo2_state_FFT3,
      I4 => NlwInverterSignal_EXP24_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_EXP24_EXP_PT_4_IN6,
      I7 => NlwInverterSignal_EXP24_EXP_PT_4_IN7,
      I8 => NlwInverterSignal_EXP24_EXP_PT_4_IN8,
      I9 => NlwInverterSignal_EXP24_EXP_PT_4_IN9,
      I10 => Inst_fifo2_cnt_val(3),
      I11 => NlwInverterSignal_EXP24_EXP_PT_4_IN11,
      I12 => NlwInverterSignal_EXP24_EXP_PT_4_IN12,
      I13 => NlwInverterSignal_EXP24_EXP_PT_4_IN13,
      I14 => NlwInverterSignal_EXP24_EXP_PT_4_IN14,
      I15 => NlwInverterSignal_EXP24_EXP_PT_4_IN15,
      I16 => Inst_fifo2_cnt_val(0),
      I17 => Inst_fifo2_cnt_val(1),
      I18 => Inst_fifo2_cnt_val(2),
      I19 => Vcc,
      I20 => Vcc,
      I21 => Vcc,
      I22 => Vcc,
      I23 => Vcc,
      I24 => Vcc,
      I25 => Vcc,
      I26 => Vcc,
      I27 => Vcc,
      I28 => Vcc,
      I29 => Vcc,
      I30 => Vcc,
      I31 => Vcc,
      O => EXP24_EXP_PT_4
    );
  EXP24_EXP_tsimrenamed_net_Q_636 : X_OR5
    port map (
      I0 => EXP24_EXP_PT_0,
      I1 => EXP24_EXP_PT_1,
      I2 => EXP24_EXP_PT_2,
      I3 => EXP24_EXP_PT_3,
      I4 => EXP24_EXP_PT_4,
      O => EXP24_EXP_tsimrenamed_net_Q
    );
  EXP25_EXP_637 : X_BUF
    port map (
      I => EXP25_EXP_tsimrenamed_net_Q,
      O => EXP25_EXP
    );
  EXP25_EXP_PT_0_638 : X_AND2
    port map (
      I0 => EXP24_EXP,
      I1 => EXP24_EXP,
      O => EXP25_EXP_PT_0
    );
  EXP25_EXP_PT_1_639 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_1_IN0,
      I1 => Inst_fifo2_cnt_val(4),
      O => EXP25_EXP_PT_1
    );
  EXP25_EXP_PT_2_640 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      I3 => Inst_fifo2_cnt_val(4),
      O => EXP25_EXP_PT_2
    );
  EXP25_EXP_PT_3_641 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      I3 => Inst_fifo2_cnt_val(4),
      O => EXP25_EXP_PT_3
    );
  EXP25_EXP_PT_4_642 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_4_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      I3 => Inst_fifo2_cnt_val(4),
      O => EXP25_EXP_PT_4
    );
  EXP25_EXP_PT_5_643 : X_AND5
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_5_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      I4 => Inst_fifo2_cnt_val(4),
      O => EXP25_EXP_PT_5
    );
  EXP25_EXP_tsimrenamed_net_Q_644 : X_OR6
    port map (
      I0 => EXP25_EXP_PT_0,
      I1 => EXP25_EXP_PT_1,
      I2 => EXP25_EXP_PT_2,
      I3 => EXP25_EXP_PT_3,
      I4 => EXP25_EXP_PT_4,
      I5 => EXP25_EXP_PT_5,
      O => EXP25_EXP_tsimrenamed_net_Q
    );
  EXP26_EXP_645 : X_BUF
    port map (
      I => EXP26_EXP_tsimrenamed_net_Q,
      O => EXP26_EXP
    );
  EXP26_EXP_PT_0_646 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP26_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP26_EXP_PT_0_IN1,
      I2 => Inst_fifo2_cnt_val(4),
      O => EXP26_EXP_PT_0
    );
  EXP26_EXP_PT_1_647 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP26_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP26_EXP_PT_1_IN1,
      I2 => Inst_fifo2_cnt_val(4),
      O => EXP26_EXP_PT_1
    );
  EXP26_EXP_PT_2_648 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP26_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP26_EXP_PT_2_IN1,
      I2 => Inst_fifo2_cnt_val(4),
      O => EXP26_EXP_PT_2
    );
  EXP26_EXP_PT_3_649 : X_AND4
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      I3 => Inst_fifo2_cnt_val(4),
      O => EXP26_EXP_PT_3
    );
  EXP26_EXP_PT_4_650 : X_AND16
    port map (
      I0 => reset_IBUF,
      I1 => Inst_fifo2_state_FFT2,
      I2 => Inst_fifo2_state_FFT1,
      I3 => NlwInverterSignal_EXP26_EXP_PT_4_IN3,
      I4 => NlwInverterSignal_EXP26_EXP_PT_4_IN4,
      I5 => NlwInverterSignal_EXP26_EXP_PT_4_IN5,
      I6 => NlwInverterSignal_EXP26_EXP_PT_4_IN6,
      I7 => Inst_fifo2_cnt_val(3),
      I8 => NlwInverterSignal_EXP26_EXP_PT_4_IN8,
      I9 => NlwInverterSignal_EXP26_EXP_PT_4_IN9,
      I10 => NlwInverterSignal_EXP26_EXP_PT_4_IN10,
      I11 => NlwInverterSignal_EXP26_EXP_PT_4_IN11,
      I12 => NlwInverterSignal_EXP26_EXP_PT_4_IN12,
      I13 => Inst_fifo2_cnt_val(0),
      I14 => Inst_fifo2_cnt_val(1),
      I15 => Inst_fifo2_cnt_val(2),
      O => EXP26_EXP_PT_4
    );
  EXP26_EXP_tsimrenamed_net_Q_651 : X_OR5
    port map (
      I0 => EXP26_EXP_PT_0,
      I1 => EXP26_EXP_PT_1,
      I2 => EXP26_EXP_PT_2,
      I3 => EXP26_EXP_PT_3,
      I4 => EXP26_EXP_PT_4,
      O => EXP26_EXP_tsimrenamed_net_Q
    );
  EXP27_EXP_652 : X_BUF
    port map (
      I => EXP27_EXP_tsimrenamed_net_Q,
      O => EXP27_EXP
    );
  EXP27_EXP_PT_0_653 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => EXP27_EXP_PT_0
    );
  EXP27_EXP_PT_1_654 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP27_EXP_PT_1_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => EXP27_EXP_PT_1
    );
  EXP27_EXP_PT_2_655 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP27_EXP_PT_2_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => EXP27_EXP_PT_2
    );
  EXP27_EXP_tsimrenamed_net_Q_656 : X_OR3
    port map (
      I0 => EXP27_EXP_PT_0,
      I1 => EXP27_EXP_PT_1,
      I2 => EXP27_EXP_PT_2,
      O => EXP27_EXP_tsimrenamed_net_Q
    );
  EXP28_EXP_657 : X_BUF
    port map (
      I => EXP28_EXP_tsimrenamed_net_Q,
      O => EXP28_EXP
    );
  EXP28_EXP_PT_0_658 : X_AND2
    port map (
      I0 => EXP27_EXP,
      I1 => EXP27_EXP,
      O => EXP28_EXP_PT_0
    );
  EXP28_EXP_PT_1_659 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP28_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP28_EXP_PT_1_IN1,
      O => EXP28_EXP_PT_1
    );
  EXP28_EXP_PT_2_660 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP28_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP28_EXP_PT_2_IN1,
      O => EXP28_EXP_PT_2
    );
  EXP28_EXP_PT_3_661 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(9),
      I1 => NlwInverterSignal_EXP28_EXP_PT_3_IN1,
      O => EXP28_EXP_PT_3
    );
  EXP28_EXP_PT_4_662 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(7),
      I1 => NlwInverterSignal_EXP28_EXP_PT_4_IN1,
      O => EXP28_EXP_PT_4
    );
  EXP28_EXP_PT_5_663 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(8),
      I1 => NlwInverterSignal_EXP28_EXP_PT_5_IN1,
      O => EXP28_EXP_PT_5
    );
  EXP28_EXP_tsimrenamed_net_Q_664 : X_OR6
    port map (
      I0 => EXP28_EXP_PT_0,
      I1 => EXP28_EXP_PT_1,
      I2 => EXP28_EXP_PT_2,
      I3 => EXP28_EXP_PT_3,
      I4 => EXP28_EXP_PT_4,
      I5 => EXP28_EXP_PT_5,
      O => EXP28_EXP_tsimrenamed_net_Q
    );
  EXP29_EXP_665 : X_BUF
    port map (
      I => EXP29_EXP_tsimrenamed_net_Q,
      O => EXP29_EXP
    );
  EXP29_EXP_PT_0_666 : X_AND2
    port map (
      I0 => EXP30_EXP,
      I1 => EXP30_EXP,
      O => EXP29_EXP_PT_0
    );
  EXP29_EXP_PT_1_667 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP29_EXP_PT_1_IN1,
      O => EXP29_EXP_PT_1
    );
  EXP29_EXP_PT_2_668 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => EXP29_EXP_PT_2
    );
  EXP29_EXP_PT_3_669 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => EXP29_EXP_PT_3
    );
  EXP29_EXP_PT_4_670 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(4),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP29_EXP_PT_4_IN2,
      O => EXP29_EXP_PT_4
    );
  EXP29_EXP_PT_5_671 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(3),
      I1 => Inst_fifo2_cnt_val(5),
      I2 => NlwInverterSignal_EXP29_EXP_PT_5_IN2,
      O => EXP29_EXP_PT_5
    );
  EXP29_EXP_tsimrenamed_net_Q_672 : X_OR6
    port map (
      I0 => EXP29_EXP_PT_0,
      I1 => EXP29_EXP_PT_1,
      I2 => EXP29_EXP_PT_2,
      I3 => EXP29_EXP_PT_3,
      I4 => EXP29_EXP_PT_4,
      I5 => EXP29_EXP_PT_5,
      O => EXP29_EXP_tsimrenamed_net_Q
    );
  EXP30_EXP_673 : X_BUF
    port map (
      I => EXP30_EXP_tsimrenamed_net_Q,
      O => EXP30_EXP
    );
  EXP30_EXP_PT_0_674 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP30_EXP_PT_0_IN1,
      I2 => NlwInverterSignal_EXP30_EXP_PT_0_IN2,
      I3 => NlwInverterSignal_EXP30_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_EXP30_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_EXP30_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_EXP30_EXP_PT_0_IN6,
      I7 => NlwInverterSignal_EXP30_EXP_PT_0_IN7,
      O => EXP30_EXP_PT_0
    );
  EXP30_EXP_PT_1_675 : X_AND8
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP30_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_EXP30_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_EXP30_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP30_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP30_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP30_EXP_PT_1_IN6,
      I7 => NlwInverterSignal_EXP30_EXP_PT_1_IN7,
      O => EXP30_EXP_PT_1
    );
  EXP30_EXP_PT_2_676 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP30_EXP_PT_2_IN1,
      I2 => NlwInverterSignal_EXP30_EXP_PT_2_IN2,
      I3 => NlwInverterSignal_EXP30_EXP_PT_2_IN3,
      I4 => NlwInverterSignal_EXP30_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP30_EXP_PT_2_IN5,
      I6 => NlwInverterSignal_EXP30_EXP_PT_2_IN6,
      I7 => NlwInverterSignal_EXP30_EXP_PT_2_IN7,
      I8 => NlwInverterSignal_EXP30_EXP_PT_2_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP30_EXP_PT_2
    );
  EXP30_EXP_PT_3_677 : X_AND16
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP30_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_EXP30_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_EXP30_EXP_PT_3_IN3,
      I4 => NlwInverterSignal_EXP30_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP30_EXP_PT_3_IN5,
      I6 => NlwInverterSignal_EXP30_EXP_PT_3_IN6,
      I7 => NlwInverterSignal_EXP30_EXP_PT_3_IN7,
      I8 => NlwInverterSignal_EXP30_EXP_PT_3_IN8,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => EXP30_EXP_PT_3
    );
  EXP30_EXP_tsimrenamed_net_Q_678 : X_OR4
    port map (
      I0 => EXP30_EXP_PT_0,
      I1 => EXP30_EXP_PT_1,
      I2 => EXP30_EXP_PT_2,
      I3 => EXP30_EXP_PT_3,
      O => EXP30_EXP_tsimrenamed_net_Q
    );
  EXP31_EXP_679 : X_BUF
    port map (
      I => EXP31_EXP_tsimrenamed_net_Q,
      O => EXP31_EXP
    );
  EXP31_EXP_PT_0_680 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => EXP31_EXP_PT_0
    );
  EXP31_EXP_PT_1_681 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_1_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => EXP31_EXP_PT_1
    );
  EXP31_EXP_PT_2_682 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_2_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => EXP31_EXP_PT_2
    );
  EXP31_EXP_PT_3_683 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_3_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => EXP31_EXP_PT_3
    );
  EXP31_EXP_PT_4_684 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_4_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => EXP31_EXP_PT_4
    );
  EXP31_EXP_tsimrenamed_net_Q_685 : X_OR5
    port map (
      I0 => EXP31_EXP_PT_0,
      I1 => EXP31_EXP_PT_1,
      I2 => EXP31_EXP_PT_2,
      I3 => EXP31_EXP_PT_3,
      I4 => EXP31_EXP_PT_4,
      O => EXP31_EXP_tsimrenamed_net_Q
    );
  EXP32_EXP_686 : X_BUF
    port map (
      I => EXP32_EXP_tsimrenamed_net_Q,
      O => EXP32_EXP
    );
  EXP32_EXP_PT_0_687 : X_AND2
    port map (
      I0 => EXP31_EXP,
      I1 => EXP31_EXP,
      O => EXP32_EXP_PT_0
    );
  EXP32_EXP_PT_1_688 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_val(9),
      I1 => NlwInverterSignal_EXP32_EXP_PT_1_IN1,
      O => EXP32_EXP_PT_1
    );
  EXP32_EXP_PT_2_689 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_2_IN0,
      I1 => Inst_fifo2_cnt_val(7),
      O => EXP32_EXP_PT_2
    );
  EXP32_EXP_PT_3_690 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_3_IN0,
      I1 => Inst_fifo2_cnt_val(8),
      O => EXP32_EXP_PT_3
    );
  EXP32_EXP_PT_4_691 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_4_IN0,
      I1 => NlwInverterSignal_EXP32_EXP_PT_4_IN1,
      O => EXP32_EXP_PT_4
    );
  EXP32_EXP_PT_5_692 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_5_IN0,
      I1 => NlwInverterSignal_EXP32_EXP_PT_5_IN1,
      O => EXP32_EXP_PT_5
    );
  EXP32_EXP_tsimrenamed_net_Q_693 : X_OR6
    port map (
      I0 => EXP32_EXP_PT_0,
      I1 => EXP32_EXP_PT_1,
      I2 => EXP32_EXP_PT_2,
      I3 => EXP32_EXP_PT_3,
      I4 => EXP32_EXP_PT_4,
      I5 => EXP32_EXP_PT_5,
      O => EXP32_EXP_tsimrenamed_net_Q
    );
  EXP33_EXP_694 : X_BUF
    port map (
      I => EXP33_EXP_tsimrenamed_net_Q,
      O => EXP33_EXP
    );
  EXP33_EXP_PT_0_695 : X_AND2
    port map (
      I0 => EXP21_EXP,
      I1 => EXP21_EXP,
      O => EXP33_EXP_PT_0
    );
  EXP33_EXP_PT_1_696 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP33_EXP_PT_1_IN1,
      O => EXP33_EXP_PT_1
    );
  EXP33_EXP_PT_2_697 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_EXP33_EXP_PT_2_IN1,
      O => EXP33_EXP_PT_2
    );
  EXP33_EXP_PT_3_698 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_EXP33_EXP_PT_3_IN1,
      O => EXP33_EXP_PT_3
    );
  EXP33_EXP_PT_4_699 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_4_IN0,
      I1 => NlwInverterSignal_EXP33_EXP_PT_4_IN1,
      O => EXP33_EXP_PT_4
    );
  EXP33_EXP_PT_5_700 : X_AND3
    port map (
      I0 => Inst_fifo2_cnt_val(4),
      I1 => NlwInverterSignal_EXP33_EXP_PT_5_IN1,
      I2 => Inst_fifo2_cnt_val(5),
      O => EXP33_EXP_PT_5
    );
  EXP33_EXP_tsimrenamed_net_Q_701 : X_OR6
    port map (
      I0 => EXP33_EXP_PT_0,
      I1 => EXP33_EXP_PT_1,
      I2 => EXP33_EXP_PT_2,
      I3 => EXP33_EXP_PT_3,
      I4 => EXP33_EXP_PT_4,
      I5 => EXP33_EXP_PT_5,
      O => EXP33_EXP_tsimrenamed_net_Q
    );
  EXP34_EXP_702 : X_BUF
    port map (
      I => EXP34_EXP_tsimrenamed_net_Q,
      O => EXP34_EXP
    );
  EXP34_EXP_PT_0_703 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP34_EXP_PT_0_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => EXP34_EXP_PT_0
    );
  EXP34_EXP_PT_1_704 : X_AND4
    port map (
      I0 => NlwInverterSignal_EXP34_EXP_PT_1_IN0,
      I1 => dr_1_IBUF,
      I2 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      I3 => dr_0_IBUF,
      O => EXP34_EXP_PT_1
    );
  EXP34_EXP_tsimrenamed_net_Q_705 : X_OR2
    port map (
      I0 => EXP34_EXP_PT_0,
      I1 => EXP34_EXP_PT_1,
      O => EXP34_EXP_tsimrenamed_net_Q
    );
  EXP35_EXP_706 : X_BUF
    port map (
      I => EXP35_EXP_tsimrenamed_net_Q,
      O => EXP35_EXP
    );
  EXP35_EXP_PT_0_707 : X_AND2
    port map (
      I0 => Inst_fifo2_cnt_ovf1,
      I1 => NlwInverterSignal_EXP35_EXP_PT_0_IN1,
      O => EXP35_EXP_PT_0
    );
  EXP35_EXP_PT_1_708 : X_AND2
    port map (
      I0 => NlwInverterSignal_EXP35_EXP_PT_1_IN0,
      I1 => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_UIM,
      O => EXP35_EXP_PT_1
    );
  EXP35_EXP_PT_2_709 : X_AND3
    port map (
      I0 => Inst_fifo2_state_FFT2,
      I1 => Inst_fifo2_state_FFT1,
      I2 => Inst_fifo2_state_FFT3,
      O => EXP35_EXP_PT_2
    );
  EXP35_EXP_PT_3_710 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP35_EXP_PT_3_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_1_IBUF,
      O => EXP35_EXP_PT_3
    );
  EXP35_EXP_PT_4_711 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP35_EXP_PT_4_IN0,
      I1 => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      I2 => dr_0_IBUF,
      O => EXP35_EXP_PT_4
    );
  EXP35_EXP_tsimrenamed_net_Q_712 : X_OR5
    port map (
      I0 => EXP35_EXP_PT_0,
      I1 => EXP35_EXP_PT_1,
      I2 => EXP35_EXP_PT_2,
      I3 => EXP35_EXP_PT_3,
      I4 => EXP35_EXP_PT_4,
      O => EXP35_EXP_tsimrenamed_net_Q
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN6 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_0_IN6
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_1_IN7
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN6
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN7 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_0_EXP_PT_2_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_2_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_2_IN8
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_3_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_3_IN8
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_4_IN8
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_D2_PT_5_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_D2_PT_5_IN8
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_4_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_4_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val_0_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_0_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_0_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val_2_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_2_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_2_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_D2_PT_3_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_D2_PT_3_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_D2_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_10_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_10_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val_1_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_1_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_1_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val_3_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_3_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_3_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN7
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_D2_PT_5_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_D2_PT_5_IN8
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_5_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_5_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_3_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_4_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_D2_PT_4_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_D2_PT_4_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_6_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_6_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_0_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_7_EXP_PT_1_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_7_EXP_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_0_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_1_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_1_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_2_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_8_EXP_PT_3_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_8_EXP_PT_3_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_D2_PT_3_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_D2_PT_3_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_D2_PT_3_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_9_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_0_IN7
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN11 : X_INV
    port map (
      I => Inst_fifo3_cnt(3),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN11
    );
  NlwInverterBlock_Inst_fifo3_cnt_3_D2_PT_1_IN12 : X_INV
    port map (
      I => Inst_fifo3_cnt(4),
      O => NlwInverterSignal_Inst_fifo3_cnt_3_D2_PT_1_IN12
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_4_D2_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_4_D2_IN7
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_5_D2_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_5_D2_IN7
    );
  NlwInverterBlock_Inst_fifo3_cnt_6_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_6_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_6_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_6_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo3_cnt_6_EXP_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_3_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_7_EXP_PT_4_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_7_EXP_PT_4_IN7
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_D_IN0 : X_INV
    port map (
      I => Inst_fifo1_cnt_0_D1,
      O => NlwInverterSignal_Inst_fifo1_cnt_0_D_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo1_cnt(0),
      O => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_D2_PT_0_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo1_cnt(0),
      O => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_0_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_RSTF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_0_RSTF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_0_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo1_cnt(1),
      O => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo1_cnt(0),
      O => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_1_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_RSTF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_1_RSTF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_1_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo1_cnt(0),
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo1_cnt(1),
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo1_cnt(2),
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_RSTF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_2_RSTF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_2_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_D2_PT_0_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_D2_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo1_cnt(4),
      O => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_D2_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo1_cnt(3),
      O => NlwInverterSignal_Inst_fifo1_cnt_3_D2_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_RSTF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_3_RSTF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_3_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_2_IN5
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN5
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_3_IN6
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN2
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN4
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN5
    );
  NlwInverterBlock_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_Inst_ren_wen_Inst_decim_cnt_2_EXP_PT_4_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_SETF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_SETF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf2_SETF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf2_SETF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_RSTF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_RSTF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_RSTF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_RSTF_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_0_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN2
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN5
    );
  NlwInverterBlock_Inst_fifo2_cnt_val_11_EXP_PT_2_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_val_11_EXP_PT_2_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_0_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN8 : X_INV
    port map (
      I => Inst_fifo3_cnt(3),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN8
    );
  NlwInverterBlock_Inst_fifo3_cnt_0_D2_PT_1_IN9 : X_INV
    port map (
      I => Inst_fifo3_cnt(4),
      O => NlwInverterSignal_Inst_fifo3_cnt_0_D2_PT_1_IN9
    );
  NlwInverterBlock_Inst_fifo1_cnt_4_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo1_cnt_4_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_cnt_4_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo1_cnt_4_RSTF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN0
    );
  NlwInverterBlock_Inst_fifo1_cnt_4_RSTF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_cnt_4_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_0_IN7
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN9 : X_INV
    port map (
      I => Inst_fifo3_cnt(3),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN9
    );
  NlwInverterBlock_Inst_fifo3_cnt_1_D2_PT_1_IN10 : X_INV
    port map (
      I => Inst_fifo3_cnt(4),
      O => NlwInverterSignal_Inst_fifo3_cnt_1_D2_PT_1_IN10
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_0_IN7
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN10 : X_INV
    port map (
      I => Inst_fifo3_cnt(3),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN10
    );
  NlwInverterBlock_Inst_fifo3_cnt_2_D2_PT_1_IN11 : X_INV
    port map (
      I => Inst_fifo3_cnt(4),
      O => NlwInverterSignal_Inst_fifo3_cnt_2_D2_PT_1_IN11
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf1_D1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_0_IN1 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_SETF_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN0
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_SETF_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN1
    );
  NlwInverterBlock_Inst_fifo2_cnt_ovf1_SETF_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_cnt_ovf1_SETF_IN2
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(5),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN4
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN5
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_0_IN6
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo3_cnt(10),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN0
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo3_cnt(6),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo3_cnt(7),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_cnt(8),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo3_cnt(9),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN4
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo3_cnt(11),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo3_cnt(3),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN6
    );
  NlwInverterBlock_Inst_fifo3_ovf4096_D2_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo3_cnt(4),
      O => NlwInverterSignal_Inst_fifo3_ovf4096_D2_PT_1_IN7
    );
  NlwInverterBlock_trigger_out_RSTF_IN0 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_trigger_out_RSTF_IN0
    );
  NlwInverterBlock_trigger_out_RSTF_IN1 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_trigger_out_RSTF_IN1
    );
  NlwInverterBlock_rst1_OBUF_D2_PT_0_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_rst1_OBUF_D2_PT_0_IN1
    );
  NlwInverterBlock_rst1_OBUF_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_rst1_OBUF_D2_PT_1_IN0
    );
  NlwInverterBlock_rst1_OBUF_D2_PT_1_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_rst1_OBUF_D2_PT_1_IN1
    );
  NlwInverterBlock_dataready_OBUF_RSTF_IN0 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_dataready_OBUF_RSTF_IN0
    );
  NlwInverterBlock_dataready_OBUF_RSTF_IN1 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_dataready_OBUF_RSTF_IN1
    );
  NlwInverterBlock_dataready_OBUF_CE_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_dataready_OBUF_CE_IN0
    );
  NlwInverterBlock_dataready_OBUF_CE_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_dataready_OBUF_CE_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT3_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo2_state_FFT3_D2_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT3_D2_PT_1_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT3_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT3_D2_PT_2_IN4 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT3_D2_PT_2_IN4
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_2_IN1 : X_INV
    port map (
      I => full3_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_2_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_3_IN4 : X_INV
    port map (
      I => dataready_OBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN3
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_4_IN4 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_4_IN4
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN0
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN2
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_5_IN3 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN3
    );
  NlwInverterBlock_Inst_fifo2_state_FFT2_D2_PT_5_IN5 : X_INV
    port map (
      I => trigmode_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT2_D2_PT_5_IN5
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_1_IN1 : X_INV
    port map (
      I => full3_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_2_IN3
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN3
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_3_IN4 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_3_IN4
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN0
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN1
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN2
    );
  NlwInverterBlock_Inst_fifo2_state_FFT1_D2_PT_4_IN3 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo2_state_FFT1_D2_PT_4_IN3
    );
  NlwInverterBlock_Inst_fifo1_state_FFD2_D2_PT_0_IN2 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_0_IN2
    );
  NlwInverterBlock_Inst_fifo1_state_FFD2_D2_PT_1_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_fifo1_state_FFD2_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo1_delay,
      O => NlwInverterSignal_Inst_fifo1_state_FFD2_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_0_IN3 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_0_IN3
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN2
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo3_state_FFD2,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN3
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_1_IN5 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_1_IN5
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN0
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo3_state_FFD2,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN3
    );
  NlwInverterBlock_Inst_fifo3_state_FFD2_D2_PT_2_IN5 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo3_state_FFD2_D2_PT_2_IN5
    );
  NlwInverterBlock_Inst_fifo3_state_FFD1_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo3_state_FFD2,
      O => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN0
    );
  NlwInverterBlock_Inst_fifo3_state_FFD1_D2_PT_0_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_0_IN1
    );
  NlwInverterBlock_Inst_fifo3_state_FFD1_D2_PT_1_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_Inst_fifo3_state_FFD1_D2_PT_1_IN1
    );
  NlwInverterBlock_Inst_trigger_synch_trig_qout_RSTF_IN0 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN0
    );
  NlwInverterBlock_Inst_trigger_synch_trig_qout_RSTF_IN1 : X_INV
    port map (
      I => trigger_out_trigger_out_RSTF_INT_UIM,
      O => NlwInverterSignal_Inst_trigger_synch_trig_qout_RSTF_IN1
    );
  NlwInverterBlock_Inst_fifo1_delay_D_IN0 : X_INV
    port map (
      I => Inst_fifo1_delay_D1,
      O => NlwInverterSignal_Inst_fifo1_delay_D_IN0
    );
  NlwInverterBlock_Inst_fifo1_delay_D2_IN1 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_Inst_fifo1_delay_D2_IN1
    );
  NlwInverterBlock_Inst_fifo1_delay_SETF_IN0 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_delay_SETF_IN0
    );
  NlwInverterBlock_Inst_fifo1_delay_SETF_IN1 : X_INV
    port map (
      I => rst1_OBUF,
      O => NlwInverterSignal_Inst_fifo1_delay_SETF_IN1
    );
  NlwInverterBlock_dflag_OBUF_D2_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_dflag_OBUF_D2_PT_0_IN0
    );
  NlwInverterBlock_dflag_OBUF_D2_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_dflag_OBUF_D2_PT_1_IN1
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN2
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN4
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN5
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN6
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN7
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN9
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN11
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN12
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN13
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN14
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_0_IN15 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_0_IN15
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN2
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN4
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN5
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN6
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN7 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN7
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN9
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN11
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN12
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN13
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN14
    );
  NlwInverterBlock_dflag_OBUF_EXP_PT_1_IN15 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_dflag_OBUF_EXP_PT_1_IN15
    );
  NlwInverterBlock_latchtrig_OBUF_D_IN0 : X_INV
    port map (
      I => latchtrig_OBUF_D1,
      O => NlwInverterSignal_latchtrig_OBUF_D_IN0
    );
  NlwInverterBlock_latchtrig_OBUF_D2_IN3 : X_INV
    port map (
      I => dataready_OBUF,
      O => NlwInverterSignal_latchtrig_OBUF_D2_IN3
    );
  NlwInverterBlock_ren1_OBUF_D_IN0 : X_INV
    port map (
      I => ren1_OBUF_D1,
      O => NlwInverterSignal_ren1_OBUF_D_IN0
    );
  NlwInverterBlock_ren2_OBUF_D_IN0 : X_INV
    port map (
      I => ren2_OBUF_D1,
      O => NlwInverterSignal_ren2_OBUF_D_IN0
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN3
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN3
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_1_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_2_IN3 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN3
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_2_IN4 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN3
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN3
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN4
    );
  NlwInverterBlock_ren2_OBUF_D2_PT_4_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_ren2_OBUF_D2_PT_4_IN5
    );
  NlwInverterBlock_rst2_OBUF_D_IN0 : X_INV
    port map (
      I => rst2_OBUF_D1,
      O => NlwInverterSignal_rst2_OBUF_D_IN0
    );
  NlwInverterBlock_rst2_OBUF_D2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_rst2_OBUF_D2_IN0
    );
  NlwInverterBlock_rst2_OBUF_D2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_rst2_OBUF_D2_IN1
    );
  NlwInverterBlock_rst2_OBUF_D2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_rst2_OBUF_D2_IN2
    );
  NlwInverterBlock_rst3_OBUF_D_IN0 : X_INV
    port map (
      I => rst3_OBUF_D1,
      O => NlwInverterSignal_rst3_OBUF_D_IN0
    );
  NlwInverterBlock_rst3_OBUF_D2_IN0 : X_INV
    port map (
      I => Inst_fifo3_state_FFD2,
      O => NlwInverterSignal_rst3_OBUF_D2_IN0
    );
  NlwInverterBlock_rst3_OBUF_D2_IN1 : X_INV
    port map (
      I => Inst_fifo3_state_FFD1,
      O => NlwInverterSignal_rst3_OBUF_D2_IN1
    );
  NlwInverterBlock_wen1_OBUF_D_IN0 : X_INV
    port map (
      I => wen1_OBUF_D1,
      O => NlwInverterSignal_wen1_OBUF_D_IN0
    );
  NlwInverterBlock_wen1_OBUF_D2_PT_0_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_wen1_OBUF_D2_PT_0_IN1
    );
  NlwInverterBlock_wen1_OBUF_D2_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo1_state_FFD2,
      O => NlwInverterSignal_wen1_OBUF_D2_PT_1_IN0
    );
  NlwInverterBlock_wen1_OBUF_D2_PT_1_IN1 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_wen1_OBUF_D2_PT_1_IN1
    );
  NlwInverterBlock_wen2_OBUF_D_IN0 : X_INV
    port map (
      I => wen2_OBUF_D1,
      O => NlwInverterSignal_wen2_OBUF_D_IN0
    );
  NlwInverterBlock_wen2_OBUF_D2_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3
    );
  NlwInverterBlock_wen2_OBUF_D2_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN1
    );
  NlwInverterBlock_wen2_OBUF_D2_PT_3_IN3 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3
    );
  NlwInverterBlock_wen2_OBUF_D2_PT_3_IN4 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4
    );
  NlwInverterBlock_wen2_OBUF_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_wen2_OBUF_EXP_PT_0_IN1
    );
  NlwInverterBlock_wen3_OBUF_D_IN0 : X_INV
    port map (
      I => wen3_OBUF_D1,
      O => NlwInverterSignal_wen3_OBUF_D_IN0
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN3
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_0_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_0_IN4
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN3
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN4
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_1_IN5
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN3
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN4
    );
  NlwInverterBlock_wen3_OBUF_EXP_PT_2_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_wen3_OBUF_EXP_PT_2_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN0
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN2
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN3
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN4
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN6
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN7
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN8 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_2_IN8
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN0
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN1
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN2
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN3
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN6
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN7
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_3_IN8
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN0
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN2
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN4
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN6
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN7
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_4_IN8
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN0
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN2
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN4
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN6
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN7
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_5_IN8
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN0
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN2
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN3
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN4
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN5
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN6
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN7
    );
  NlwInverterBlock_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN9 : X_INV
    port map (
      I => n1_0_IBUF,
      O => NlwInverterSignal_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_D2_PT_6_IN9
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN7
    );
  NlwInverterBlock_EXP10_EXP_PT_0_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP10_EXP_PT_0_IN8
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN7
    );
  NlwInverterBlock_EXP10_EXP_PT_1_IN9 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_EXP10_EXP_PT_1_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN7
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN8
    );
  NlwInverterBlock_EXP11_EXP_PT_0_IN9 : X_INV
    port map (
      I => n1_0_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_0_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN7
    );
  NlwInverterBlock_EXP11_EXP_PT_1_IN9 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_1_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN7
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN8 : X_INV
    port map (
      I => n1_0_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN8
    );
  NlwInverterBlock_EXP11_EXP_PT_2_IN9 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_2_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN3
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN6
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN9 : X_INV
    port map (
      I => n1_0_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_3_IN10 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_3_IN10
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN3
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN6
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN9 : X_INV
    port map (
      I => n1_0_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN9
    );
  NlwInverterBlock_EXP11_EXP_PT_4_IN10 : X_INV
    port map (
      I => n1_1_IBUF,
      O => NlwInverterSignal_EXP11_EXP_PT_4_IN10
    );
  NlwInverterBlock_EXP12_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP12_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP12_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP12_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP12_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP12_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP12_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP12_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP12_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP12_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP12_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP12_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP12_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP12_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP13_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP13_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP13_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP13_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP13_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP13_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP13_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP13_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP13_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP13_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP13_EXP_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP13_EXP_PT_5_IN2
    );
  NlwInverterBlock_EXP14_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP14_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP14_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP14_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP15_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP15_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP15_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP15_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN3
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN6
    );
  NlwInverterBlock_EXP15_EXP_PT_3_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP15_EXP_PT_3_IN7
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN3
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN6
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN7
    );
  NlwInverterBlock_EXP15_EXP_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP15_EXP_PT_4_IN8
    );
  NlwInverterBlock_EXP16_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP16_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP16_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP16_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP16_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP16_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP16_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP16_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP16_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP16_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP16_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP16_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP16_EXP_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP16_EXP_PT_5_IN1
    );
  NlwInverterBlock_EXP17_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP17_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP17_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP17_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP17_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP17_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP17_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP17_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP17_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP17_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP17_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP17_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_EXP18_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_EXP18_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_EXP18_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP18_EXP_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf2,
      O => NlwInverterSignal_EXP18_EXP_PT_5_IN1
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP19_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP19_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP19_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP19_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP19_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_3_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP19_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP19_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_4_IN4 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_4_IN5 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP19_EXP_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP19_EXP_PT_5_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_5_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP19_EXP_PT_5_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_5_IN5 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_EXP19_EXP_PT_5_IN5
    );
  NlwInverterBlock_EXP19_EXP_PT_5_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_EXP19_EXP_PT_5_IN6
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => acqen_IBUF,
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP21_EXP_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP21_EXP_PT_0_IN7
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP21_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP21_EXP_PT_1_IN7
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP21_EXP_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP21_EXP_PT_2_IN7
    );
  NlwInverterBlock_EXP22_EXP_PT_0_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP22_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP22_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP22_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP22_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP22_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN8
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN9
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN10
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN11
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN12
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN8
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN9
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN10
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN11
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN12
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN6 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN8
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN10
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN11
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN12
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN13
    );
  NlwInverterBlock_EXP23_EXP_PT_4_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP23_EXP_PT_4_IN14
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN2
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN5
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN8
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN10
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN11
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN12
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN13
    );
  NlwInverterBlock_EXP23_EXP_PT_5_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP23_EXP_PT_5_IN14
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN8
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN9
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN10
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN11
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN12
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN6 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN7
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN8
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN10
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN11
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN12
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN13
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN14
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN5 : X_INV
    port map (
      I => dr_1_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN6 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN7
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN8
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN10
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN11
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN12
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN13
    );
  NlwInverterBlock_EXP24_EXP_PT_2_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP24_EXP_PT_2_IN14
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN7 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(2),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN7
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN8
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN9
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN11
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN12
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN13
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN14
    );
  NlwInverterBlock_EXP24_EXP_PT_3_IN15 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP24_EXP_PT_3_IN15
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(0),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_Inst_ren_wen_Inst_decim_cnt(1),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN7 : X_INV
    port map (
      I => dr_0_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN7
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN8
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN9
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN11
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN12
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN13 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN13
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN14 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN14
    );
  NlwInverterBlock_EXP24_EXP_PT_4_IN15 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP24_EXP_PT_4_IN15
    );
  NlwInverterBlock_EXP25_EXP_PT_1_IN0 : X_INV
    port map (
      I => reset_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP25_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP25_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP25_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP25_EXP_PT_5_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP26_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP26_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP26_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN3 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN3
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN4
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN5
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN6
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN8
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN9 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN9
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN10 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN10
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN11 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN11
    );
  NlwInverterBlock_EXP26_EXP_PT_4_IN12 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP26_EXP_PT_4_IN12
    );
  NlwInverterBlock_EXP27_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP27_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP27_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP27_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP28_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP28_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP28_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP28_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP28_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP28_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP28_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP28_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP28_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP28_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP28_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP28_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP28_EXP_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP28_EXP_PT_5_IN1
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP29_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP29_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP29_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_4_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP29_EXP_PT_4_IN2
    );
  NlwInverterBlock_EXP29_EXP_PT_5_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP29_EXP_PT_5_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN7
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(5),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN7
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN3
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN7
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN8
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(9),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(4),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN2 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(10),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN3 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN3
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN4 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(6),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN5 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(7),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN6 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(8),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN6
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN7 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(11),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN7
    );
  NlwInverterBlock_EXP30_EXP_PT_3_IN8 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP30_EXP_PT_3_IN8
    );
  NlwInverterBlock_EXP31_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP31_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP31_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP31_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP31_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP31_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP31_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP31_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP32_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP32_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP32_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP32_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP32_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(0),
      O => NlwInverterSignal_EXP32_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP32_EXP_PT_5_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP32_EXP_PT_5_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(1),
      O => NlwInverterSignal_EXP32_EXP_PT_5_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT2,
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP33_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_3_IN1 : X_INV
    port map (
      I => Inst_fifo2_state_FFT3,
      O => NlwInverterSignal_EXP33_EXP_PT_3_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP33_EXP_PT_4_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_4_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(2),
      O => NlwInverterSignal_EXP33_EXP_PT_4_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_5_IN1 : X_INV
    port map (
      I => Inst_fifo2_cnt_val(3),
      O => NlwInverterSignal_EXP33_EXP_PT_5_IN1
    );
  NlwInverterBlock_EXP34_EXP_PT_0_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP34_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP34_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP34_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP35_EXP_PT_0_IN1 : X_INV
    port map (
      I => Q_OpTx_Inst_fifo2_n0025_Inst_fifo2_n0025_D2_INV_345_UIM,
      O => NlwInverterSignal_EXP35_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP35_EXP_PT_1_IN0 : X_INV
    port map (
      I => Inst_fifo2_cnt_ovf1,
      O => NlwInverterSignal_EXP35_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP35_EXP_PT_3_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP35_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP35_EXP_PT_4_IN0 : X_INV
    port map (
      I => Inst_fifo2_state_FFT1,
      O => NlwInverterSignal_EXP35_EXP_PT_4_IN0
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;