-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Mon Jun 12 18:11:29 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY chnctrl_tbw IS
END chnctrl_tbw;

ARCHITECTURE testbench_arch OF chnctrl_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT chnctrl
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			trigmode : In  std_logic;
			decim_ratio : In  std_logic_vector (1 DOWNTO 0);
			ptrig_data : In  std_logic_vector (1 DOWNTO 0);
			acqen : In  std_logic;
			trigger : In  std_logic;
			rstdataready : In  std_logic;
			full3 : In  std_logic;
			rst1 : Out  std_logic;
			wen1 : Out  std_logic;
			ren1 : Out  std_logic;
			rst2 : Out  std_logic;
			wen2 : Out  std_logic;
			ren2 : Out  std_logic;
			rst3 : Out  std_logic;
			wen3 : Out  std_logic;
			latchtrig : Out  std_logic;
			dflag : Out  std_logic;
			dataready : Out  std_logic
		);
	END COMPONENT;

	-- inputs
	SIGNAL reset : std_logic := '0';
	SIGNAL clk : std_logic := '1';
	SIGNAL trigmode : std_logic:='0';
	SIGNAL decim_ratio : std_logic_vector (1 DOWNTO 0):="00";
	SIGNAL ptrig_data : std_logic_vector (1 DOWNTO 0):="00";
	SIGNAL acqen : std_logic := '1';
	SIGNAL trigger : std_logic:='0';
	SIGNAL rstdataready : std_logic:='1';
	SIGNAL full3 : std_logic:='1';
	
	-- outputs
	SIGNAL rst1 : std_logic;
	SIGNAL wen1 : std_logic;
	SIGNAL ren1 : std_logic;
	SIGNAL rst2 : std_logic;
	SIGNAL wen2 : std_logic;
	SIGNAL ren2 : std_logic;
	SIGNAL rst3 : std_logic;
	SIGNAL wen3 : std_logic;
	SIGNAL latchtrig : std_logic;
	SIGNAL dflag : std_logic;
	SIGNAL dataready : std_logic;

BEGIN
	UUT : chnctrl
	PORT MAP (
		reset => reset,
		clk => clk,
		trigmode => trigmode,
		decim_ratio => decim_ratio,
		ptrig_data => ptrig_data,
		acqen => acqen,
		trigger => trigger,
		rstdataready => rstdataready,
		full3 => full3,
		rst1 => rst1,
		wen1 => wen1,
		ren1 => ren1,
		rst2 => rst2,
		wen2 => wen2,
		ren2 => ren2,
		rst3 => rst3,
		wen3 => wen3,
		latchtrig => latchtrig,
		dflag => dflag,
		dataready => dataready
	);

	clk<=not clk after 50 ns;
	reset<='1' after 300 ns;

	acqen<='0' after 500 ns;

	trigger<='1' after 56 us,'0' after 57 us;
	

end testbench_arch;