cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: chnctrl Date: 7-24-2006, 4:06PM Device Used: XC95144XL-5-TQ100 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 54 /144 ( 37%) 344 /720 ( 48%) 42 /144 ( 29%) 22 /81 ( 27%) 125/432 ( 29%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 8 8 | I/O : 19 54 Output : 11 11 | GCK/IO : 2 1 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 2 2 | GSR/IO : 1 0 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 22 22 MACROCELL RESOURCES: Total Macrocells Available 144 Registered Macrocells 42 Non-registered Macrocell driving I/O 9 GLOBAL RESOURCES: Signal 'clk' mapped onto global clock net GCK1. Signal 'trigger' mapped onto global clock net GCK2. Global output enable net(s) unused. Signal 'reset' mapped onto global set/reset net GSR. POWER DATA: There are 54 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 54 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 2 3 FB6_11 STD 80 I/O (b) SET Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 2 4 FB6_10 STD (b) (b) SET Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> 2 5 FB6_9 STD 79 I/O (b) SET Inst_fsm1/cnt_delay<0> 5 8 FB6_17 STD 86 I/O (b) SET Inst_fsm1/cnt_delay<1> 5 8 FB6_16 STD (b) (b) SET Inst_fsm1/cnt_delay<2> 4 8 FB6_14 STD 82 I/O (b) SET Inst_fsm1/cnt_delay<3> 3 8 FB6_13 STD (b) (b) SET Inst_fsm1/cnt_delay<4> 2 8 FB6_8 STD 78 I/O (b) SET Inst_fsm1/cnt_delay_ovf 3 8 FB6_12 STD 81 I/O (b) RESET Inst_fsm1/cnt_record<0> 11 20 FB3_17 STD 34 I/O (b) SET Inst_fsm1/cnt_record<10> 11 22 FB4_7 STD (b) (b) SET Inst_fsm1/cnt_record<11> 6 22 FB8_18 STD (b) (b) SET Inst_fsm1/cnt_record<1> 12 21 FB8_16 STD (b) (b) SET Inst_fsm1/cnt_record<2> 13 22 FB8_10 STD (b) (b) SET Inst_fsm1/cnt_record<3> 13 21 FB8_13 STD (b) (b) SET Inst_fsm1/cnt_record<4> 14 22 FB8_7 STD (b) (b) SET Inst_fsm1/cnt_record<5> 15 22 FB8_3 STD (b) (b) SET Inst_fsm1/cnt_record<6> 16 22 FB4_12 STD 94 I/O I SET Inst_fsm1/cnt_record<7> 17 22 FB4_17 STD 97 I/O (b) SET Inst_fsm1/cnt_record<8> 18 22 FB4_2 STD 87 I/O (b) SET Inst_fsm1/cnt_record<9> 16 22 FB4_10 STD (b) (b) SET Inst_fsm1/cnt_record_ovf 19 21 FB3_2 STD 23 GCK/I/O GCK RESET Inst_fsm1/cnt_record_ptrg 11 15 FB5_17 STD 49 I/O (b) RESET Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2 4 FB6_7 STD (b) (b) Inst_fsm1/cnt_transfer<0> 5 13 FB2_9 STD 4 GTS/I/O (b) SET Inst_fsm1/cnt_transfer<10> 3 15 FB2_5 STD 1 GTS/I/O (b) SET Inst_fsm1/cnt_transfer<11> 2 15 FB2_2 STD 99 GSR/I/O GSR/I SET Inst_fsm1/cnt_transfer<1> 6 14 FB2_12 STD 7 I/O I SET Inst_fsm1/cnt_transfer<2> 7 15 FB2_16 STD (b) (b) SET Inst_fsm1/cnt_transfer<3> 7 14 FB2_15 STD 9 I/O (b) SET Inst_fsm1/cnt_transfer<4> 8 15 FB2_1 STD (b) (b) SET Inst_fsm1/cnt_transfer<5> 8 15 FB2_18 STD (b) (b) SET Inst_fsm1/cnt_transfer<6> 7 15 FB2_13 STD (b) (b) SET Inst_fsm1/cnt_transfer<7> 6 15 FB2_10 STD (b) (b) SET Inst_fsm1/cnt_transfer<8> 5 15 FB2_8 STD 3 GTS/I/O (b) SET Inst_fsm1/cnt_transfer<9> 4 15 FB2_7 STD (b) (b) SET Inst_fsm1/cnt_transfer_ovf 4 13 FB2_6 STD 2 GTS/I/O (b) RESET Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF 2 4 FB6_6 STD 77 I/O (b) Inst_fsm1/state_FFT2 6 10 FB6_18 STD (b) (b) RESET Inst_fsm1/state_FFT3 5 9 FB6_15 STD 85 I/O (b) RESET Inst_trigger_synch/trig_qout 3 4 FB2_4 STD (b) (b) RESET dataready 3 6 FB2_11 STD FAST 6 I/O O RESET dflag 5 9 FB6_5 STD FAST 76 I/O O RESET latchtrig 1 3 FB3_6 STD FAST 25 I/O O ren1 3 3 FB5_11 STD FAST 41 I/O O ren2 5 9 FB8_17 STD FAST 73 I/O O rst1 1 3 FB5_12 STD FAST 42 I/O O rst2 1 3 FB8_15 STD FAST 72 I/O O rst3 1 3 FB8_9 STD FAST 67 I/O O trigger_out 3 5 FB2_3 STD (b) (b) RESET trigger_out/trigger_out_RSTF__$INT 1 2 FB6_4 STD (b) (b) wen1 3 3 FB5_9 STD FAST 40 I/O O wen2 6 9 FB4_15 STD FAST 96 I/O O wen3 1 2 FB4_14 STD FAST 95 I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use acqen FB2_14 8 I/O I clk FB1_17 22 GCK/I/O GCK decim_ratio<0> FB1_6 14 I/O I decim_ratio<1> FB1_5 13 I/O I full3 FB4_12 94 I/O I ptrig_data<0> FB1_9 16 I/O I ptrig_data<1> FB1_8 15 I/O I reset FB2_2 99 GSR/I/O GSR/I rstdataready FB2_12 7 I/O I trigger FB3_2 23 GCK/I/O GCK trigmode FB1_3 12 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 0 0 0 0 0/0 11 FB2 16 21 21 81 1/0 10 FB3 3 21 21 31 1/0 10 FB4 7 22 22 85 2/0 10 FB5 4 18 18 18 3/0 10 FB6 15 21 21 49 1/0 10 FB7 0 0 0 0 0/0 10 FB8 9 22 22 80 3/0 10 ---- ----- ----- ----- 54 344 11/0 81 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 11 I/O (unused) 0 0 0 5 FB1_3 12 I/O I (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 13 I/O I (unused) 0 0 0 5 FB1_6 14 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 15 I/O I (unused) 0 0 0 5 FB1_9 16 I/O I (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 17 I/O (unused) 0 0 0 5 FB1_12 18 I/O (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 19 I/O (unused) 0 0 0 5 FB1_15 20 I/O (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 22 GCK/I/O GCK (unused) 0 0 0 5 FB1_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use Inst_fsm1/cnt_transfer<4> 8 3<- 0 0 FB2_1 STD (b) (b) Inst_fsm1/cnt_transfer<11> 2 0 /\3 0 FB2_2 STD 99 GSR/I/O GSR/I trigger_out 3 0 0 2 FB2_3 STD (b) (b) Inst_trigger_synch/trig_qout 3 0 0 2 FB2_4 STD (b) (b) Inst_fsm1/cnt_transfer<10> 3 0 0 2 FB2_5 STD 1 GTS/I/O (b) Inst_fsm1/cnt_transfer_ovf 4 0 \/1 0 FB2_6 STD 2 GTS/I/O (b) Inst_fsm1/cnt_transfer<9> 4 1<- \/2 0 FB2_7 STD (b) (b) Inst_fsm1/cnt_transfer<8> 5 2<- \/2 0 FB2_8 STD 3 GTS/I/O (b) Inst_fsm1/cnt_transfer<0> 5 2<- \/2 0 FB2_9 STD 4 GTS/I/O (b) Inst_fsm1/cnt_transfer<7> 6 2<- \/1 0 FB2_10 STD (b) (b) dataready 3 1<- \/3 0 FB2_11 STD 6 I/O O Inst_fsm1/cnt_transfer<1> 6 3<- \/2 0 FB2_12 STD 7 I/O I Inst_fsm1/cnt_transfer<6> 7 2<- 0 0 FB2_13 STD (b) (b) (unused) 0 0 \/4 1 FB2_14 8 I/O I Inst_fsm1/cnt_transfer<3> 7 4<- \/2 0 FB2_15 STD 9 I/O (b) Inst_fsm1/cnt_transfer<2> 7 2<- 0 0 FB2_16 STD (b) (b) (unused) 0 0 \/3 2 FB2_17 10 I/O (b) Inst_fsm1/cnt_transfer<5> 8 3<- 0 0 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/cnt_transfer<0> 8: Inst_fsm1/cnt_transfer<5> 15: Inst_fsm1/state_FFT2 2: Inst_fsm1/cnt_transfer<10> 9: Inst_fsm1/cnt_transfer<6> 16: Inst_fsm1/state_FFT3 3: Inst_fsm1/cnt_transfer<11> 10: Inst_fsm1/cnt_transfer<7> 17: Inst_trigger_synch/trig_qout 4: Inst_fsm1/cnt_transfer<1> 11: Inst_fsm1/cnt_transfer<8> 18: dataready 5: Inst_fsm1/cnt_transfer<2> 12: Inst_fsm1/cnt_transfer<9> 19: dflag 6: Inst_fsm1/cnt_transfer<3> 13: Inst_fsm1/cnt_transfer_ovf 20: rstdataready 7: Inst_fsm1/cnt_transfer<4> 14: Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF 21: trigger_out/trigger_out_RSTF__$INT Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Inst_fsm1/cnt_transfer<4> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer<11> XXXXXXXXXXXX.XX...X..................... 15 15 trigger_out ..............XXX.X.X................... 5 5 Inst_trigger_synch/trig_qout ..............XX..X.X................... 4 4 Inst_fsm1/cnt_transfer<10> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer_ovf .XX.XXXXXXXX.XX...X..................... 13 13 Inst_fsm1/cnt_transfer<9> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer<8> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer<0> .XX.XXXXXXXX.XX...X..................... 13 13 Inst_fsm1/cnt_transfer<7> XXXXXXXXXXXX.XX...X..................... 15 15 dataready ............X.XX.XXX.................... 6 6 Inst_fsm1/cnt_transfer<1> XXX.XXXXXXXX.XX...X..................... 14 14 Inst_fsm1/cnt_transfer<6> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer<3> XXXXX.XXXXXX.XX...X..................... 14 14 Inst_fsm1/cnt_transfer<2> XXXXXXXXXXXX.XX...X..................... 15 15 Inst_fsm1/cnt_transfer<5> XXXXXXXXXXXX.XX...X..................... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 \/5 0 FB3_1 (b) (b) Inst_fsm1/cnt_record_ovf 19 14<- 0 0 FB3_2 STD 23 GCK/I/O GCK (unused) 0 0 /\5 0 FB3_3 (b) (b) (unused) 0 0 /\4 1 FB3_4 (b) (b) (unused) 0 0 0 5 FB3_5 24 I/O latchtrig 1 0 0 4 FB3_6 STD 25 I/O O (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 27 GCK/I/O (unused) 0 0 0 5 FB3_9 28 I/O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 29 I/O (unused) 0 0 0 5 FB3_12 30 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 32 I/O (unused) 0 0 0 5 FB3_15 33 I/O (unused) 0 0 \/1 4 FB3_16 (b) (b) Inst_fsm1/cnt_record<0> 11 6<- 0 0 FB3_17 STD 34 I/O (b) (unused) 0 0 /\5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 8: Inst_fsm1/cnt_record<4> 15: Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 9: Inst_fsm1/cnt_record<5> 16: Inst_fsm1/state_FFT2 3: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> 10: Inst_fsm1/cnt_record<6> 17: Inst_fsm1/state_FFT3 4: Inst_fsm1/cnt_record<10> 11: Inst_fsm1/cnt_record<7> 18: decim_ratio<0> 5: Inst_fsm1/cnt_record<11> 12: Inst_fsm1/cnt_record<8> 19: decim_ratio<1> 6: Inst_fsm1/cnt_record<2> 13: Inst_fsm1/cnt_record<9> 20: dflag 7: Inst_fsm1/cnt_record<3> 14: Inst_fsm1/cnt_record_ovf 21: reset Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Inst_fsm1/cnt_record_ovf XXXXXXXXXXXXXXXXXXXXX................... 21 21 latchtrig ...............XX..X.................... 3 3 Inst_fsm1/cnt_record<0> XXXXXXXXXXXXX.XXXXXXX................... 20 20 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 \/5 0 FB4_1 (b) (b) Inst_fsm1/cnt_record<8> 18 13<- 0 0 FB4_2 STD 87 I/O (b) (unused) 0 0 /\5 0 FB4_3 (b) (b) (unused) 0 0 /\3 2 FB4_4 (b) (b) (unused) 0 0 \/3 2 FB4_5 89 I/O (b) (unused) 0 0 \/5 0 FB4_6 90 I/O (b) Inst_fsm1/cnt_record<10> 11 8<- \/2 0 FB4_7 STD (b) (b) (unused) 0 0 \/5 0 FB4_8 91 I/O (b) (unused) 0 0 \/5 0 FB4_9 92 I/O (b) Inst_fsm1/cnt_record<9> 16 12<- \/1 0 FB4_10 STD (b) (b) (unused) 0 0 \/5 0 FB4_11 93 I/O (b) Inst_fsm1/cnt_record<6> 16 11<- 0 0 FB4_12 STD 94 I/O I (unused) 0 0 /\5 0 FB4_13 (b) (b) wen3 1 0 \/3 1 FB4_14 STD 95 I/O O wen2 6 3<- \/2 0 FB4_15 STD 96 I/O O (unused) 0 0 \/5 0 FB4_16 (b) (b) Inst_fsm1/cnt_record<7> 17 12<- 0 0 FB4_17 STD 97 I/O (b) (unused) 0 0 /\5 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 9: Inst_fsm1/cnt_record<3> 16: Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 10: Inst_fsm1/cnt_record<4> 17: Inst_fsm1/state_FFT2 3: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> 11: Inst_fsm1/cnt_record<5> 18: Inst_fsm1/state_FFT3 4: Inst_fsm1/cnt_record<0> 12: Inst_fsm1/cnt_record<6> 19: decim_ratio<0> 5: Inst_fsm1/cnt_record<10> 13: Inst_fsm1/cnt_record<7> 20: decim_ratio<1> 6: Inst_fsm1/cnt_record<11> 14: Inst_fsm1/cnt_record<8> 21: dflag 7: Inst_fsm1/cnt_record<1> 15: Inst_fsm1/cnt_record<9> 22: reset 8: Inst_fsm1/cnt_record<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Inst_fsm1/cnt_record<8> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 Inst_fsm1/cnt_record<10> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 Inst_fsm1/cnt_record<9> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 Inst_fsm1/cnt_record<6> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 wen3 ................X...X................... 2 2 wen2 XXX.............XXXXXX.................. 9 9 Inst_fsm1/cnt_record<7> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 35 I/O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 36 I/O (unused) 0 0 0 5 FB5_6 37 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 39 I/O wen1 3 0 0 2 FB5_9 STD 40 I/O O (unused) 0 0 0 5 FB5_10 (b) ren1 3 0 0 2 FB5_11 STD 41 I/O O rst1 1 0 0 4 FB5_12 STD 42 I/O O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 43 I/O (unused) 0 0 0 5 FB5_15 46 I/O (unused) 0 0 \/1 4 FB5_16 (b) (b) Inst_fsm1/cnt_record_ptrg 11 6<- 0 0 FB5_17 STD 49 I/O (b) (unused) 0 0 /\5 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/cnt_record<0> 7: Inst_fsm1/cnt_record<4> 13: Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2: Inst_fsm1/cnt_record<10> 8: Inst_fsm1/cnt_record<5> 14: Inst_fsm1/state_FFT2 3: Inst_fsm1/cnt_record<11> 9: Inst_fsm1/cnt_record<6> 15: Inst_fsm1/state_FFT3 4: Inst_fsm1/cnt_record<1> 10: Inst_fsm1/cnt_record<7> 16: dflag 5: Inst_fsm1/cnt_record<2> 11: Inst_fsm1/cnt_record<8> 17: ptrig_data<0> 6: Inst_fsm1/cnt_record<3> 12: Inst_fsm1/cnt_record<9> 18: ptrig_data<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs wen1 .............XXX........................ 3 3 ren1 .............XXX........................ 3 3 rst1 .............XXX........................ 3 3 Inst_fsm1/cnt_record_ptrg XXXXXXXXXXXXX...XX...................... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 /\1 4 FB6_1 (b) (b) (unused) 0 0 0 5 FB6_2 74 I/O (unused) 0 0 0 5 FB6_3 (b) trigger_out/trigger_out_RSTF__$INT 1 0 0 4 FB6_4 STD (b) (b) dflag 5 0 0 0 FB6_5 STD 76 I/O O Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF 2 0 0 3 FB6_6 STD 77 I/O (b) Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2 0 0 3 FB6_7 STD (b) (b) Inst_fsm1/cnt_delay<4> 2 0 0 3 FB6_8 STD 78 I/O (b) Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> 2 0 0 3 FB6_9 STD 79 I/O (b) Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 2 0 0 3 FB6_10 STD (b) (b) Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 2 0 0 3 FB6_11 STD 80 I/O (b) Inst_fsm1/cnt_delay_ovf 3 0 0 2 FB6_12 STD 81 I/O (b) Inst_fsm1/cnt_delay<3> 3 0 0 2 FB6_13 STD (b) (b) Inst_fsm1/cnt_delay<2> 4 0 0 1 FB6_14 STD 82 I/O (b) Inst_fsm1/state_FFT3 5 0 0 0 FB6_15 STD 85 I/O (b) Inst_fsm1/cnt_delay<1> 5 0 0 0 FB6_16 STD (b) (b) Inst_fsm1/cnt_delay<0> 5 0 0 0 FB6_17 STD 86 I/O (b) Inst_fsm1/state_FFT2 6 1<- 0 0 FB6_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 8: Inst_fsm1/cnt_delay_ovf 15: dataready 2: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 9: Inst_fsm1/cnt_record_ovf 16: dflag 3: Inst_fsm1/cnt_delay<0> 10: Inst_fsm1/cnt_record_ptrg 17: full3 4: Inst_fsm1/cnt_delay<1> 11: Inst_fsm1/cnt_transfer_ovf 18: reset 5: Inst_fsm1/cnt_delay<2> 12: Inst_fsm1/state_FFT2 19: rstdataready 6: Inst_fsm1/cnt_delay<3> 13: Inst_fsm1/state_FFT3 20: trigger_out 7: Inst_fsm1/cnt_delay<4> 14: acqen 21: trigmode Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs trigger_out/trigger_out_RSTF__$INT .................XX..................... 2 2 dflag ...........XXXXXX.XXX................... 9 9 Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF ...........XX..X..X..................... 4 4 Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF ..........XXX..X........................ 4 4 Inst_fsm1/cnt_delay<4> ..XXXXX....XX..X........................ 8 8 Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> XX.........XX..X........................ 5 5 Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> X..........XX..X........................ 4 4 Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> ...........XX..X........................ 3 3 Inst_fsm1/cnt_delay_ovf ..XXXXX....XX..X........................ 8 8 Inst_fsm1/cnt_delay<3> ..XXXXX....XX..X........................ 8 8 Inst_fsm1/cnt_delay<2> ..XXXXX....XX..X........................ 8 8 Inst_fsm1/state_FFT3 .......X.XXXXX.XX...X................... 9 9 Inst_fsm1/cnt_delay<1> ..XXXXX....XX..X........................ 8 8 Inst_fsm1/cnt_delay<0> ..XXXXX....XX..X........................ 8 8 Inst_fsm1/state_FFT2 .......XX.XXXX.XX.X.X................... 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 50 I/O (unused) 0 0 0 5 FB7_3 (b) (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 52 I/O (unused) 0 0 0 5 FB7_6 53 I/O (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 54 I/O (unused) 0 0 0 5 FB7_9 55 I/O (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 56 I/O (unused) 0 0 0 5 FB7_12 58 I/O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 59 I/O (unused) 0 0 0 5 FB7_15 60 I/O (unused) 0 0 0 5 FB7_16 (b) (unused) 0 0 0 5 FB7_17 61 I/O (unused) 0 0 0 5 FB7_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 22/32 Number of signals used by logic mapping into function block: 22 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 /\4 1 FB8_1 (b) (b) (unused) 0 0 \/5 0 FB8_2 63 I/O (b) Inst_fsm1/cnt_record<5> 15 10<- 0 0 FB8_3 STD (b) (b) (unused) 0 0 /\5 0 FB8_4 (b) (b) (unused) 0 0 0 5 FB8_5 64 I/O (unused) 0 0 \/4 1 FB8_6 65 I/O (b) Inst_fsm1/cnt_record<4> 14 9<- 0 0 FB8_7 STD (b) (b) (unused) 0 0 /\5 0 FB8_8 66 I/O (b) rst3 1 0 \/3 1 FB8_9 STD 67 I/O O Inst_fsm1/cnt_record<2> 13 8<- 0 0 FB8_10 STD (b) (b) (unused) 0 0 /\5 0 FB8_11 68 I/O (b) (unused) 0 0 \/5 0 FB8_12 70 I/O (b) Inst_fsm1/cnt_record<3> 13 8<- 0 0 FB8_13 STD (b) (b) (unused) 0 0 /\3 2 FB8_14 71 I/O (b) rst2 1 0 \/4 0 FB8_15 STD 72 I/O O Inst_fsm1/cnt_record<1> 12 7<- 0 0 FB8_16 STD (b) (b) ren2 5 3<- /\3 0 FB8_17 STD 73 I/O O Inst_fsm1/cnt_record<11> 6 4<- /\3 0 FB8_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> 9: Inst_fsm1/cnt_record<3> 16: Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF 2: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> 10: Inst_fsm1/cnt_record<4> 17: Inst_fsm1/state_FFT2 3: Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> 11: Inst_fsm1/cnt_record<5> 18: Inst_fsm1/state_FFT3 4: Inst_fsm1/cnt_record<0> 12: Inst_fsm1/cnt_record<6> 19: decim_ratio<0> 5: Inst_fsm1/cnt_record<10> 13: Inst_fsm1/cnt_record<7> 20: decim_ratio<1> 6: Inst_fsm1/cnt_record<11> 14: Inst_fsm1/cnt_record<8> 21: dflag 7: Inst_fsm1/cnt_record<1> 15: Inst_fsm1/cnt_record<9> 22: reset 8: Inst_fsm1/cnt_record<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Inst_fsm1/cnt_record<5> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 Inst_fsm1/cnt_record<4> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 rst3 ................XX..X................... 3 3 Inst_fsm1/cnt_record<2> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 Inst_fsm1/cnt_record<3> XXXXXXXX.XXXXXXXXXXXXX.................. 21 21 rst2 ................XX..X................... 3 3 Inst_fsm1/cnt_record<1> XXXXXX.XXXXXXXXXXXXXXX.................. 21 21 ren2 XXX.............XXXXXX.................. 9 9 Inst_fsm1/cnt_record<11> XXXXXXXXXXXXXXXXXXXXXX.................. 22 22 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0>.T = dflag & !Inst_fsm1/state_FFT3 # !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0>.CLK = clk; // GCK !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0>.AR = reset; // GSR Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1>.T = Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & Inst_fsm1/state_FFT2; Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1>.CLK = clk; // GCK !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1>.AR = reset; // GSR Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2>.T = Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & Inst_fsm1/state_FFT2; Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2>.CLK = clk; // GCK !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2>.AR = reset; // GSR !Inst_fsm1/cnt_delay<0>.T = dflag # Inst_fsm1/state_FFT2 # !Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & Inst_fsm1/cnt_delay<2> & Inst_fsm1/cnt_delay<3> & Inst_fsm1/cnt_delay<4>; Inst_fsm1/cnt_delay<0>.CLK = clk; // GCK Inst_fsm1/cnt_delay<0>.AR = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<1>.T = Inst_fsm1/cnt_delay<0> & !Inst_fsm1/cnt_delay<1> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & !Inst_fsm1/cnt_delay<2> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & !Inst_fsm1/cnt_delay<3> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & !Inst_fsm1/cnt_delay<4> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<1>.CLK = clk; // GCK Inst_fsm1/cnt_delay<1>.AR = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<2>.T = Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & !Inst_fsm1/cnt_delay<2> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & !Inst_fsm1/cnt_delay<3> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & !Inst_fsm1/cnt_delay<4> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<2>.CLK = clk; // GCK Inst_fsm1/cnt_delay<2>.AR = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<3>.T = Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & Inst_fsm1/cnt_delay<2> & !Inst_fsm1/cnt_delay<3> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & Inst_fsm1/cnt_delay<2> & !Inst_fsm1/cnt_delay<4> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<3>.CLK = clk; // GCK Inst_fsm1/cnt_delay<3>.AR = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<4>.T = Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & Inst_fsm1/cnt_delay<2> & Inst_fsm1/cnt_delay<3> & !Inst_fsm1/cnt_delay<4> & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay<4>.CLK = clk; // GCK Inst_fsm1/cnt_delay<4>.AR = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !Inst_fsm1/cnt_delay_ovf.D = Inst_fsm1/cnt_delay<0> & Inst_fsm1/cnt_delay<1> & Inst_fsm1/cnt_delay<2> & Inst_fsm1/cnt_delay<3> & Inst_fsm1/cnt_delay<4>; Inst_fsm1/cnt_delay_ovf.CLK = clk; // GCK Inst_fsm1/cnt_delay_ovf.AP = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/cnt_delay_ovf.CE = !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; !Inst_fsm1/cnt_record<0>.T = !reset # !Inst_fsm1/state_FFT2 # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 ;Imported pterms FB3_16 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> ;Imported pterms FB3_18 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8>; Inst_fsm1/cnt_record<0>.CLK = clk; // GCK Inst_fsm1/cnt_record<0>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; Inst_fsm1/cnt_record<10>.T = Inst_fsm1/cnt_record<9> & !Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 ;Imported pterms FB4_6 # Inst_fsm1/cnt_record<9> & !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & !Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 ;Imported pterms FB4_5 # Inst_fsm1/cnt_record<9> & !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> # Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0>; Inst_fsm1/cnt_record<10>.CLK = clk; // GCK Inst_fsm1/cnt_record<10>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; Inst_fsm1/cnt_record<11>.T = Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 ;Imported pterms FB8_1 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0>; Inst_fsm1/cnt_record<11>.CLK = clk; // GCK Inst_fsm1/cnt_record<11>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<1>.T = Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !Inst_fsm1/state_FFT3 & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> ;Imported pterms FB8_15 # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/state_FFT3 & decim_ratio<1> ;Imported pterms FB8_17 # !reset # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_record<1>.CLK = clk; // GCK Inst_fsm1/cnt_record<1>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<2>.T = Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !Inst_fsm1/state_FFT3 & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> ;Imported pterms FB8_9 # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/state_FFT3 & decim_ratio<1> ;Imported pterms FB8_11 # !reset # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1> # !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8>; Inst_fsm1/cnt_record<2>.CLK = clk; // GCK Inst_fsm1/cnt_record<2>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<3>.T = Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/state_FFT3 & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !Inst_fsm1/state_FFT3 & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> ;Imported pterms FB8_12 # !Inst_fsm1/cnt_record<2> # !Inst_fsm1/state_FFT2 # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/state_FFT3 & decim_ratio<1> ;Imported pterms FB8_14 # !reset # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1>; Inst_fsm1/cnt_record<3>.CLK = clk; // GCK Inst_fsm1/cnt_record<3>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<4>.T = !reset # !Inst_fsm1/cnt_record<2> # !Inst_fsm1/cnt_record<3> # !Inst_fsm1/state_FFT2 ;Imported pterms FB8_6 # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1> # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 ;Imported pterms FB8_8 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8>; Inst_fsm1/cnt_record<4>.CLK = clk; // GCK Inst_fsm1/cnt_record<4>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<5>.T = !Inst_fsm1/cnt_record<2> # !Inst_fsm1/cnt_record<3> # !Inst_fsm1/cnt_record<4> # !Inst_fsm1/state_FFT2 ;Imported pterms FB8_2 # !reset # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1> # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 ;Imported pterms FB8_4 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8>; Inst_fsm1/cnt_record<5>.CLK = clk; // GCK Inst_fsm1/cnt_record<5>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<6>.T = !Inst_fsm1/cnt_record<2> # !Inst_fsm1/cnt_record<3> # !Inst_fsm1/cnt_record<4> # !Inst_fsm1/cnt_record<5> ;Imported pterms FB4_11 # !reset # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1> # !Inst_fsm1/state_FFT2 # !dflag & Inst_fsm1/state_FFT3 ;Imported pterms FB4_10 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> ;Imported pterms FB4_13 # dflag & !Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1>; Inst_fsm1/cnt_record<6>.CLK = clk; // GCK Inst_fsm1/cnt_record<6>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<7>.T = !Inst_fsm1/cnt_record<2> # !Inst_fsm1/cnt_record<4> # !Inst_fsm1/cnt_record<5> # !Inst_fsm1/cnt_record<6> ;Imported pterms FB4_16 # !reset # !Inst_fsm1/cnt_record<3> # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/cnt_record<1> # !Inst_fsm1/state_FFT2 ;Imported pterms FB4_15 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> ;Imported pterms FB4_18 # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1>; Inst_fsm1/cnt_record<7>.CLK = clk; // GCK Inst_fsm1/cnt_record<7>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record<8>.T = !Inst_fsm1/cnt_record<4> # !Inst_fsm1/cnt_record<5> # !Inst_fsm1/cnt_record<6> # !Inst_fsm1/cnt_record<7> ;Imported pterms FB4_1 # !reset # !Inst_fsm1/cnt_record<2> # !Inst_fsm1/cnt_record<3> # !Inst_fsm1/cnt_record<0> # !Inst_fsm1/state_FFT2 ;Imported pterms FB4_3 # !Inst_fsm1/cnt_record<1> # dflag & !Inst_fsm1/state_FFT3 # !dflag & Inst_fsm1/state_FFT3 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & decim_ratio<1> ;Imported pterms FB4_4 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<8> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & decim_ratio<0> & decim_ratio<1>; Inst_fsm1/cnt_record<8>.CLK = clk; // GCK Inst_fsm1/cnt_record<8>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; Inst_fsm1/cnt_record<9>.T = !Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # !Inst_fsm1/cnt_record<9> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # !Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 ;Imported pterms FB4_9 # !Inst_fsm1/cnt_record<9> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # !Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # !Inst_fsm1/cnt_record<9> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> ;Imported pterms FB4_8 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # !Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> ;Imported pterms FB4_7 # !Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # reset & !Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_fsm1/cnt_record<9>.CLK = clk; // GCK Inst_fsm1/cnt_record<9>.AR = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record_ovf.D = !reset & !Inst_fsm1/cnt_record_ovf # !Inst_fsm1/cnt_record_ovf & !Inst_fsm1/state_FFT2 # !Inst_fsm1/cnt_record_ovf & dflag & !Inst_fsm1/state_FFT3 # !Inst_fsm1/cnt_record_ovf & !dflag & Inst_fsm1/state_FFT3 ;Imported pterms FB3_1 # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record_ovf & !dflag & decim_ratio<0> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/cnt_record_ovf & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/cnt_record_ovf & !dflag & decim_ratio<1> # Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !Inst_fsm1/cnt_record_ovf & !dflag & decim_ratio<0> & decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 ;Imported pterms FB3_3 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> ;Imported pterms FB3_4 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & !decim_ratio<0>; Inst_fsm1/cnt_record_ovf.CLK = clk; // GCK Inst_fsm1/cnt_record_ovf.AP = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; !Inst_fsm1/cnt_record_ptrg.D = Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<11> # Inst_fsm1/cnt_record<10> & !ptrig_data<1> # Inst_fsm1/cnt_record<11> & !ptrig_data<0> # Inst_fsm1/cnt_record<11> & !ptrig_data<1> ;Imported pterms FB5_16 # Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<11> ;Imported pterms FB5_18 # Inst_fsm1/cnt_record<9> & !ptrig_data<0> & !ptrig_data<1> # Inst_fsm1/cnt_record<11> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !ptrig_data<1> # Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !ptrig_data<0> & !ptrig_data<1> # Inst_fsm1/cnt_record<9> & Inst_fsm1/cnt_record<10> & Inst_fsm1/cnt_record<2> & Inst_fsm1/cnt_record<3> & Inst_fsm1/cnt_record<4> & Inst_fsm1/cnt_record<5> & Inst_fsm1/cnt_record<6> & Inst_fsm1/cnt_record<7> & Inst_fsm1/cnt_record<8> & Inst_fsm1/cnt_record<0> & Inst_fsm1/cnt_record<1> & !ptrig_data<0>; Inst_fsm1/cnt_record_ptrg.CLK = clk; // GCK Inst_fsm1/cnt_record_ptrg.AP = Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF; Inst_fsm1/cnt_record_ptrg/Inst_fsm1/cnt_record_ptrg_SETF = !Inst_fsm1/cnt_transfer_ovf # !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !Inst_fsm1/cnt_transfer<0>.T = !dflag # Inst_fsm1/state_FFT2 ;Imported pterms FB2_8 # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer<0>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<0>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<10>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<10>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<10>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<11>.T = Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<11>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<11>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; !Inst_fsm1/cnt_transfer<1>.T = !dflag # Inst_fsm1/state_FFT2 ;Imported pterms FB2_11 # !Inst_fsm1/cnt_transfer<0> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer<1>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<1>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; !Inst_fsm1/cnt_transfer<2>.T = !Inst_fsm1/cnt_transfer<0> # !Inst_fsm1/cnt_transfer<1> # !dflag # Inst_fsm1/state_FFT2 ;Imported pterms FB2_15 # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer<2>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<2>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; !Inst_fsm1/cnt_transfer<3>.T = !Inst_fsm1/cnt_transfer<2> # !dflag ;Imported pterms FB2_14 # !Inst_fsm1/cnt_transfer<0> # !Inst_fsm1/cnt_transfer<1> # Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer<3>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<3>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; !Inst_fsm1/cnt_transfer<4>.T = !Inst_fsm1/cnt_transfer<2> # !Inst_fsm1/cnt_transfer<3> # !dflag # Inst_fsm1/state_FFT2 ;Imported pterms FB2_2 # !Inst_fsm1/cnt_transfer<0> # !Inst_fsm1/cnt_transfer<1> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer<4>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<4>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<5>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & !Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & !Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & !Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 ;Imported pterms FB2_17 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & !Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & !Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<5>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<5>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<6>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & !Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & !Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & !Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 ;Imported pterms FB2_12 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & !Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<6>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<6>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<7>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & !Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & !Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 ;Imported pterms FB2_9 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & !Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<7>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<7>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<8>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & !Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 ;Imported pterms FB2_7 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & !Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<8>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<8>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer<9>.T = !Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & !Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<0> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2 ;Imported pterms FB2_6 # Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<0> & !Inst_fsm1/cnt_transfer<11> & Inst_fsm1/cnt_transfer<1> & dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer<9>.CLK = clk; // GCK Inst_fsm1/cnt_transfer<9>.AR = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; !Inst_fsm1/cnt_transfer_ovf.D = Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<2> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11> # Inst_fsm1/cnt_transfer<10> & Inst_fsm1/cnt_transfer<3> & Inst_fsm1/cnt_transfer<4> & Inst_fsm1/cnt_transfer<5> & Inst_fsm1/cnt_transfer<6> & Inst_fsm1/cnt_transfer<7> & Inst_fsm1/cnt_transfer<8> & Inst_fsm1/cnt_transfer<9> & Inst_fsm1/cnt_transfer<11>; Inst_fsm1/cnt_transfer_ovf.CLK = clk; // GCK Inst_fsm1/cnt_transfer_ovf.AP = Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF; Inst_fsm1/cnt_transfer_ovf.CE = dflag & !Inst_fsm1/state_FFT2; Inst_fsm1/cnt_transfer_ovf/Inst_fsm1/cnt_transfer_ovf_SETF = !rstdataready # !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; Inst_fsm1/state_FFT2.T = Inst_fsm1/state_FFT2 & !full3 # Inst_fsm1/state_FFT2 & acqen # !Inst_fsm1/cnt_record_ovf & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # !Inst_fsm1/cnt_transfer_ovf & dflag & !Inst_fsm1/state_FFT2 & full3 & !acqen # trigmode & !rstdataready & dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 ;Imported pterms FB6_1 # !Inst_fsm1/cnt_delay_ovf & !dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & full3 & !acqen; Inst_fsm1/state_FFT2.CLK = clk; // GCK !Inst_fsm1/state_FFT2.AR = reset; // GSR Inst_fsm1/state_FFT3.D = Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & full3 & !acqen # Inst_fsm1/cnt_transfer_ovf & dflag & Inst_fsm1/state_FFT3 & full3 & !acqen # Inst_fsm1/cnt_delay_ovf & !dflag & Inst_fsm1/state_FFT3 & full3 & !acqen # !dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/cnt_record_ptrg & full3 & !acqen # !trigmode & !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & full3 & !acqen; Inst_fsm1/state_FFT3.CLK = clk; // GCK !Inst_fsm1/state_FFT3.AR = reset; // GSR Inst_trigger_synch/trig_qout.D = !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; Inst_trigger_synch/trig_qout.CLK = trigger; // GCK Inst_trigger_synch/trig_qout.AR = !trigger_out/trigger_out_RSTF__$INT; Inst_trigger_synch/trig_qout.CE = !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; !dataready.D = !rstdataready # Inst_fsm1/cnt_transfer_ovf & !dataready ;Imported pterms FB2_10 # !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; dataready.CLK = clk; // GCK dflag.T = dflag & !full3 # dflag & acqen # !trigmode & !rstdataready & dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # trigmode & !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 & full3 & !acqen # trigger_out & !dflag & !dataready & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & full3 & !acqen; dflag.CLK = clk; // GCK !dflag.AR = reset; // GSR !latchtrig = !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; !ren1 = !dflag & Inst_fsm1/state_FFT2 # Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !ren2 = reset & dflag & !Inst_fsm1/state_FFT2 # reset & !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & !decim_ratio<0> & !decim_ratio<1> ;Imported pterms FB8_18 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & !decim_ratio<1> # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 & !decim_ratio<0>; !rst3 = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !rst2 = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !rst1 = !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; trigger_out.D = Inst_trigger_synch/trig_qout; trigger_out.CLK = clk; // GCK trigger_out.AR = !trigger_out/trigger_out_RSTF__$INT; trigger_out.CE = !dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3; trigger_out/trigger_out_RSTF__$INT = reset & rstdataready; wen1 = dflag & Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # dflag & !Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # !dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3; !wen2 = reset & dflag & Inst_fsm1/state_FFT2 & Inst_fsm1/state_FFT3 # reset & dflag & !Inst_fsm1/state_FFT2 & !Inst_fsm1/state_FFT3 # reset & !dflag & Inst_fsm1/state_FFT2 & !decim_ratio<0> & !decim_ratio<1> ;Imported pterms FB4_14 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !dflag & Inst_fsm1/state_FFT2 & !decim_ratio<1> # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<2> & !dflag & Inst_fsm1/state_FFT2 # reset & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<0> & !Inst_fsm1/Inst_ren_wen/Inst_decim/cnt<1> & !dflag & Inst_fsm1/state_FFT2 & !decim_ratio<0>; !wen3 = dflag & !Inst_fsm1/state_FFT2; Legend: .COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC95144XL-5-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-5-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 51 VCC 2 TIE 52 TIE 3 TIE 53 TIE 4 TIE 54 TIE 5 VCC 55 TIE 6 dataready 56 TIE 7 rstdataready 57 VCC 8 acqen 58 TIE 9 TIE 59 TIE 10 TIE 60 TIE 11 TIE 61 TIE 12 trigmode 62 GND 13 decim_ratio<1> 63 TIE 14 decim_ratio<0> 64 TIE 15 ptrig_data<1> 65 TIE 16 ptrig_data<0> 66 TIE 17 TIE 67 rst3 18 TIE 68 TIE 19 TIE 69 GND 20 TIE 70 TIE 21 GND 71 TIE 22 clk 72 rst2 23 trigger 73 ren2 24 TIE 74 TIE 25 latchtrig 75 GND 26 VCC 76 dflag 27 TIE 77 TIE 28 TIE 78 TIE 29 TIE 79 TIE 30 TIE 80 TIE 31 GND 81 TIE 32 TIE 82 TIE 33 TIE 83 TDO 34 TIE 84 GND 35 TIE 85 TIE 36 TIE 86 TIE 37 TIE 87 TIE 38 VCC 88 VCC 39 TIE 89 TIE 40 wen1 90 TIE 41 ren1 91 TIE 42 rst1 92 TIE 43 TIE 93 TIE 44 GND 94 full3 45 TDI 95 wen3 46 TIE 96 wen2 47 TMS 97 TIE 48 TCK 98 VCC 49 TIE 99 reset 50 TIE 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-5-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 50