-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 8.2i -- \ \ Application : ISE -- / / Filename : chn_ctrl_tb0.vhw -- /___/ /\ Timestamp : Mon Mar 12 16:02:00 2007 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: chn_ctrl_tb0 --Device: Xilinx -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY chn_ctrl_tb0 IS END chn_ctrl_tb0; ARCHITECTURE testbench_arch OF chn_ctrl_tb0 IS FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt"; COMPONENT chnctrl PORT ( reset : In std_logic; clk : In std_logic; trigmode : In std_logic; decim_ratio : In std_logic_vector (1 DownTo 0); ptrig_data : In std_logic_vector (1 DownTo 0); acqen : In std_logic; trigger : In std_logic; rstdataready : In std_logic; full3 : In std_logic; rst1 : Out std_logic; wen1 : Out std_logic; ren1 : Out std_logic; rst2 : Out std_logic; wen2 : Out std_logic; ren2 : Out std_logic; rst3 : Out std_logic; wen3 : Out std_logic; latchtrig : Out std_logic; dflag : Out std_logic; dataready : Out std_logic ); END COMPONENT; SIGNAL reset : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL trigmode : std_logic := '0'; SIGNAL decim_ratio : std_logic_vector (1 DownTo 0) := "00"; SIGNAL ptrig_data : std_logic_vector (1 DownTo 0) := "00"; SIGNAL acqen : std_logic := '0'; SIGNAL trigger : std_logic := '1'; SIGNAL rstdataready : std_logic := '0'; SIGNAL full3 : std_logic := '0'; SIGNAL rst1 : std_logic := '0'; SIGNAL wen1 : std_logic := '0'; SIGNAL ren1 : std_logic := '0'; SIGNAL rst2 : std_logic := '0'; SIGNAL wen2 : std_logic := '0'; SIGNAL ren2 : std_logic := '0'; SIGNAL rst3 : std_logic := '0'; SIGNAL wen3 : std_logic := '0'; SIGNAL latchtrig : std_logic := '0'; SIGNAL dflag : std_logic := '0'; SIGNAL dataready : std_logic := '0'; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; constant PERIOD : time := 20 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 100 ns; BEGIN UUT : chnctrl PORT MAP ( reset => reset, clk => clk, trigmode => trigmode, decim_ratio => decim_ratio, ptrig_data => ptrig_data, acqen => acqen, trigger => trigger, rstdataready => rstdataready, full3 => full3, rst1 => rst1, wen1 => wen1, ren1 => ren1, rst2 => rst2, wen2 => wen2, ren2 => ren2, rst3 => rst3, wen3 => wen3, latchtrig => latchtrig, dflag => dflag, dataready => dataready ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS PROCEDURE CHECK_dataready( next_dataready : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (dataready /= next_dataready) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns dataready=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, dataready); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_dataready); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_dflag( next_dflag : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (dflag /= next_dflag) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns dflag=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, dflag); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_dflag); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_latchtrig( next_latchtrig : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (latchtrig /= next_latchtrig) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns latchtrig=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, latchtrig); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_latchtrig); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_ren1( next_ren1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (ren1 /= next_ren1) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns ren1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ren1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_ren2( next_ren2 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (ren2 /= next_ren2) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns ren2=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren2); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ren2); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_rst1( next_rst1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (rst1 /= next_rst1) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns rst1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rst1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_rst2( next_rst2 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (rst2 /= next_rst2) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns rst2=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst2); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rst2); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_rst3( next_rst3 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (rst3 /= next_rst3) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns rst3=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst3); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rst3); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_wen1( next_wen1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (wen1 /= next_wen1) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns wen1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wen1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_wen2( next_wen2 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (wen2 /= next_wen2) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns wen2=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen2); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wen2); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_wen3( next_wen3 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN IF (wen3 /= next_wen3) THEN STD.TEXTIO.write(TX_LOC, string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'("ns wen3=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen3); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wen3); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; BEGIN -- ------------- Current Time: 105ns WAIT FOR 105 ns; trigmode <= '1'; acqen <= '1'; full3 <= '1'; -- ------------------------------------- -- ------------- Current Time: 225ns WAIT FOR 120 ns; rstdataready <= '1'; -- ------------------------------------- -- ------------- Current Time: 265ns WAIT FOR 40 ns; reset <= '1'; -- ------------------------------------- -- ------------- Current Time: 725ns WAIT FOR 460 ns; acqen <= '0'; -- ------------------------------------- WAIT FOR 9295 ns; IF (TX_ERROR = 0) THEN STD.TEXTIO.write(TX_OUT, string'("No errors or warnings")); STD.TEXTIO.writeline(RESULTS, TX_OUT); ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected." SEVERITY FAILURE; ELSE STD.TEXTIO.write(TX_OUT, TX_ERROR); STD.TEXTIO.write(TX_OUT, string'(" errors found in simulation")); STD.TEXTIO.writeline(RESULTS, TX_OUT); ASSERT (FALSE) REPORT "Errors found during simulation" SEVERITY FAILURE; END IF; END PROCESS; END testbench_arch;