version 3
U:/Projects/SAO/VHDL/Latestfiles/ChannelCtrl/Chnctrl/chnctrl.vhd
chnctrl
VHDL
VHDL
chn_ctrl_tb0.xwv
Clocked
-
-
10000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
10000000
10000000
5000000
5000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
acqen
clk
dataready
clk
decim_ratio
clk
dflag
clk
full3
clk
latchtrig
clk
ptrig_data
clk
ren1
clk
ren2
clk
reset
clk
rst1
clk
rst2
clk
rst3
clk
rstdataready
clk
trigger
clk
trigmode
clk
wen1
clk
wen2
clk
wen3
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
dataready_DIFF
dflag_DIFF
latchtrig_DIFF
ren1_DIFF
ren2_DIFF
rst1_DIFF
rst2_DIFF
rst3_DIFF
wen1_DIFF
wen2_DIFF
wen3_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
acqen
full3
reset
rstdataready
trigger
trigmode
decim_ratio
ptrig_data
dataready
dflag
latchtrig
ren1
ren2
rst1
rst2
rst3
wen1
wen2
wen3
SIGNAL_ORDER_END
-X-X-X-