ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... ERROR:NgdBuild:755 - Line 4 in 'chnctrl.ucf': Could not find net(s) 'acqclk' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 7 in 'chnctrl.ucf': Could not find net(s) 'decim_flag' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 8 in 'chnctrl.ucf': Could not find net(s) 'decim_ratio<0>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 9 in 'chnctrl.ucf': Could not find net(s) 'decim_ratio<1>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 10 in 'chnctrl.ucf': Could not find net(s) 'empty2' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 11 in 'chnctrl.ucf': Could not find net(s) 'fsmst<0>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 12 in 'chnctrl.ucf': Could not find net(s) 'fsmst<1>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 13 in 'chnctrl.ucf': Could not find net(s) 'fsmst<2>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 14 in 'chnctrl.ucf': Could not find net(s) 'full2' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 15 in 'chnctrl.ucf': Could not find net(s) 'latch_en' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 16 in 'chnctrl.ucf': Could not find net(s) 'n1param<0>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 17 in 'chnctrl.ucf': Could not find net(s) 'n1param<1>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 23 in 'chnctrl.ucf': Could not find net(s) 'trig_mode' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 24 in 'chnctrl.ucf': Could not find net(s) 'trigger_in' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 25 in 'chnctrl.ucf': Could not find net(s) 'tx_read' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "chnctrl.ucf". Writing NGDBUILD log file "chnctrl.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9572XL-5-VQ44. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks....................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal trigger_out/trigger_out_RSTF__$INT. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9572XL-5-VQ44. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks....................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal trigger_out/trigger_out_RSTF__$INT. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks....................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal trigger_out/trigger_out_RSTF__$INT. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. Considering device XC9572XL-5-TQ100. Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks...............................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal Inst_fifo3/cnt<8>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. . Considering device XC95144XL-5-TQ100. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............................................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 590. ... The number of paths traced: 1181. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks....................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal trigger_out/trigger_out_RSTF__$INT. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. Considering device XC9572XL-5-TQ100. Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks...............................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal Inst_fifo3/cnt<8>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. . Considering device XC95144XL-5-TQ100. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............................................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 590. ... The number of paths traced: 1181. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # ** Error: chnctrl.vhd(127): near "<": expecting: <= := # ** Error: chnctrl.vhd(127): near ";": expecting: <= := # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./chnctrl_tbw.ado line 17 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 349 # Stopped at chnctrl_tbw.ant line 349 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0010> created at line 155. Found 12-bit comparator greatequal for signal <$n0011> created at line 155. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 8 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0028> created at line 386. Found 12-bit comparator less for signal <$n0029> created at line 392. Found 12-bit adder for signal <$n0035> created at line 390. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 10 1-bit register : 7 3-bit register : 1 12-bit register : 1 5-bit register : 1 # Counters : 1 12-bit up counter : 1 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 6 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val_8 implementation constraint: INIT=s : cnt_val_9 implementation constraint: INIT=s : cnt_val_7 implementation constraint: INIT=s : cnt_val_6 implementation constraint: INIT=s : cnt_val_11 implementation constraint: INIT=s : cnt_val_10 implementation constraint: INIT=s : cnt_val_0 implementation constraint: INIT=s : cnt_val_1 implementation constraint: INIT=s : cnt_val_2 implementation constraint: INIT=s : cnt_val_3 implementation constraint: INIT=s : cnt_val_4 implementation constraint: INIT=s : cnt_val_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks.............................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal Inst_fifo3/cnt<7>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. .. Considering device XC9572XL-5-TQ100. Re-checking device resources ... Mapping a total of 57 equations into 4 function blocks..............................................................................................................................................................................................................ERROR:Cpld:892 - Cannot place signal Inst_fifo3/cnt<8>. Consider reducing the collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions. . Considering device XC95144XL-5-TQ100. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............................................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............................................. (Location of error unknown)XSLT Error (java.io.FileNotFoundException): chnctrl_pad.csv (The process cannot access the file because it is being used by another process) Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.26.Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : chnctrl_locked.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............................................. (Location of error unknown)XSLT Error (java.io.FileNotFoundException): chnctrl_pad.csv (The process cannot access the file because it is being used by another process) Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.26.Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : chnctrl.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0010> created at line 155. Found 12-bit comparator greatequal for signal <$n0011> created at line 155. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 8 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0028> created at line 386. Found 12-bit comparator less for signal <$n0029> created at line 392. Found 12-bit adder for signal <$n0035> created at line 390. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 10 1-bit register : 7 3-bit register : 1 12-bit register : 1 5-bit register : 1 # Counters : 1 12-bit up counter : 1 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 6 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val_8 implementation constraint: INIT=s : cnt_val_9 implementation constraint: INIT=s : cnt_val_7 implementation constraint: INIT=s : cnt_val_6 implementation constraint: INIT=s : cnt_val_11 implementation constraint: INIT=s : cnt_val_10 implementation constraint: INIT=s : cnt_val_0 implementation constraint: INIT=s : cnt_val_1 implementation constraint: INIT=s : cnt_val_2 implementation constraint: INIT=s : cnt_val_3 implementation constraint: INIT=s : cnt_val_4 implementation constraint: INIT=s : cnt_val_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 55 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. ERROR:Cpld:832 - 'dataready' is assigned to an invalid location ('PIN74') for this device. This will prevent the design from fitting on the current device. 'dataready' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'ren2' is assigned to an invalid location ('PIN64') for this device. This will prevent the design from fitting on the current device. 'ren2' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'rst2' is assigned to an invalid location ('PIN16') for this device. This will prevent the design from fitting on the current device. 'rst2' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'rst3' is assigned to an invalid location ('PIN87') for this device. This will prevent the design from fitting on the current device. 'rst3' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'wen1' is assigned to an invalid location ('PIN41') for this device. This will prevent the design from fitting on the current device. 'wen1' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'wen2' is assigned to an invalid location ('PIN52') for this device. This will prevent the design from fitting on the current device. 'wen2' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'wen3' is assigned to an invalid location ('PIN93') for this device. This will prevent the design from fitting on the current device. 'wen3' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'reset' is assigned to an invalid location ('PIN99') for this device. This will prevent the design from fitting on the current device. 'reset' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'n1<1>' is assigned to an invalid location ('PIN71') for this device. This will prevent the design from fitting on the current device. 'n1<1>' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'dr<0>' is assigned to an invalid location ('PIN30') for this device. This will prevent the design from fitting on the current device. 'dr<0>' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'rstdataready' is assigned to an invalid location ('PIN63') for this device. This will prevent the design from fitting on the current device. 'rstdataready' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'trigmode' is assigned to an invalid location ('PIN59') for this device. This will prevent the design from fitting on the current device. 'trigmode' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'acqen' is assigned to an invalid location ('PIN80') for this device. This will prevent the design from fitting on the current device. 'acqen' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'dr<1>' is assigned to an invalid location ('PIN89') for this device. This will prevent the design from fitting on the current device. 'dr<1>' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'full3' is assigned to an invalid location ('PIN96') for this device. This will prevent the design from fitting on the current device. 'full3' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'trigger' is assigned to an invalid location ('PIN23') for this device. This will prevent the design from fitting on the current device. 'trigger' must be reassigned before attempting a re-fit. Considering device XC9572XL-5-TQ100. ERROR:Cpld:832 - 'ren1' is assigned to an invalid location ('PIN24') for this device. This will prevent the design from fitting on the current device. 'ren1' must be reassigned before attempting a re-fit. ERROR:Cpld:832 - 'acqen' is assigned to an invalid location ('PIN80') for this device. This will prevent the design from fitting on the current device. 'acqen' must be reassigned before attempting a re-fit. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 2 5-bit register : 1 1-bit register : 1 # Adders/Subtractors : 1 5-bit adder : 1 # Comparators : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl fifo1.ngc fifo1.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 33420 kilobytes Writing NGD file "fifo1.ngd" ... Writing NGDBUILD log file "fifo1.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 10 equations into 8 function blocks................. Design fifo1 has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 81. The number of paths traced: 163. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock clk ... fifo1.tim has been created. Generating Stamp model files fifo1.mod, fifo1.data ... fifo1.mod has been created. fifo1.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.26.Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : chnctrl.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks............... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks.............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Lock Pins". pin2ucf: Xilinx Pin Locker G.26.Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Pin Locking constraints file generated in : chnctrl.ucf Completed process "Lock Pins". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks.............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35468 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks.............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do trigger_sync_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity trigger_sync_tbw # -- Compiling architecture testbench_arch of trigger_sync_tbw # -- Loading entity trigger_synch # -- Compiling configuration trigger_synch_cfg # -- Loading entity trigger_sync_tbw # -- Loading architecture testbench_arch of trigger_sync_tbw # vsim -lib work -t 1ps trigger_sync_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.trigger_sync_tbw(testbench_arch) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 330 ns Iteration: 0 Process: /trigger_sync_tbw/line__83 File: trigger_sync_tbw.ant # Break at trigger_sync_tbw.ant line 104 # Stopped at trigger_sync_tbw.ant line 104 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0010> created at line 155. Found 12-bit comparator greatequal for signal <$n0011> created at line 155. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 8 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0028> created at line 386. Found 12-bit comparator less for signal <$n0029> created at line 392. Found 12-bit adder for signal <$n0035> created at line 390. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 10 1-bit register : 7 3-bit register : 1 12-bit register : 1 5-bit register : 1 # Counters : 1 12-bit up counter : 1 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 6 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val_8 implementation constraint: INIT=s : cnt_val_9 implementation constraint: INIT=s : cnt_val_7 implementation constraint: INIT=s : cnt_val_6 implementation constraint: INIT=s : cnt_val_11 implementation constraint: INIT=s : cnt_val_10 implementation constraint: INIT=s : cnt_val_0 implementation constraint: INIT=s : cnt_val_1 implementation constraint: INIT=s : cnt_val_2 implementation constraint: INIT=s : cnt_val_3 implementation constraint: INIT=s : cnt_val_4 implementation constraint: INIT=s : cnt_val_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks.............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design chnctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist chnctrl_timesim.vhd ... Writing VHDL SDF file chnctrl_timesim.sdf ... Total memory usage is 33804 kilobytes Created netgen log file 'chnctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0010> created at line 155. Found 12-bit comparator greatequal for signal <$n0011> created at line 155. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 8 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0028> created at line 386. Found 12-bit comparator less for signal <$n0029> created at line 392. Found 12-bit adder for signal <$n0035> created at line 390. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 10 1-bit register : 7 3-bit register : 1 12-bit register : 1 5-bit register : 1 # Counters : 1 12-bit up counter : 1 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 6 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val_8 implementation constraint: INIT=s : cnt_val_9 implementation constraint: INIT=s : cnt_val_7 implementation constraint: INIT=s : cnt_val_6 implementation constraint: INIT=s : cnt_val_11 implementation constraint: INIT=s : cnt_val_10 implementation constraint: INIT=s : cnt_val_0 implementation constraint: INIT=s : cnt_val_1 implementation constraint: INIT=s : cnt_val_2 implementation constraint: INIT=s : cnt_val_3 implementation constraint: INIT=s : cnt_val_4 implementation constraint: INIT=s : cnt_val_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 57 equations into 8 function blocks.............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ....... The number of paths traced: 598. ... The number of paths traced: 1197. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 186. Undefined symbol 'cnt_en'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 302. cnt_en: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 417. parse error, unexpected IF, expecting PROCESS ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 456. parse error, unexpected IF, expecting PROCESS Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # ** Error: fifo2.vhd(186): Illegal target for signal assignment. # ** Error: fifo2.vhd(186): Unknown identifier: cnt_en # ** Error: fifo2.vhd(186): Target of signal assignment is not a signal. # ** Error: fifo2.vhd(302): Illegal target for signal assignment. # ** Error: fifo2.vhd(302): Unknown identifier: cnt_en # ** Error: fifo2.vhd(302): Target of signal assignment is not a signal. # ** Error: fifo2.vhd(329): Illegal target for signal assignment. # ** Error: fifo2.vhd(329): Unknown identifier: cnt_en # ** Error: fifo2.vhd(329): Target of signal assignment is not a signal. # ** Error: fifo2.vhd(347): Illegal target for signal assignment. # ** Error: fifo2.vhd(347): Unknown identifier: cnt_en # ** Error: fifo2.vhd(347): Target of signal assignment is not a signal. # ** Error: fifo2.vhd(417): near "if": expecting: PROCESS # ** Error: fifo2.vhd(456): near "if": expecting: PROCESS # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./fifo2ctrl_tbw.ado line 12 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 303. Undefined symbol 'cnt_en'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 330. cnt_en: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 418. parse error, unexpected IF, expecting PROCESS ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 457. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 331. Undefined symbol 'cnt_en'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 349. cnt_en: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 419. parse error, unexpected IF, expecting PROCESS ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 458. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 350. Undefined symbol 'cnt_en'. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 420. parse error, unexpected IF, expecting PROCESS ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 459. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 421. parse error, unexpected IF, expecting PROCESS ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 460. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd Line 459. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # ** Error: fifo2.vhd(439): Unknown identifier: n1_val2 # ** Error: fifo2.vhd(439): Bad expression. # ** Error: fifo2.vhd(439): Type error resolving infix expression. # ** Error: fifo2.vhd(484): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./fifo2ctrl_tbw.ado line 12 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 269 # Stopped at fifo2ctrl_tbw.ant line 269 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__218 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 281 # Stopped at fifo2ctrl_tbw.ant line 281 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # WARNING[1]: chnctrl.vhd(166): Port "rstdataready" is on entity "fifo3" used for default binding, but is not on the component declaration. # WARNING[1]: chnctrl.vhd(166): A use of this default binding for this component instantiation will result in an elaboration error. # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Port "rstdataready" is on entity "fifo3" used for default binding, but is not on the component declaration of line 166. # Time: 0 ps Iteration: 0 Instance: /chnctrl_tbw/uut File: chnctrl.vhd # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # Fatal error at dffen.vhd line 31 # while elaborating region: /chnctrl_tbw/uut/inst_trigger_synch/inst_dffen1 # Load interrupted # Error loading design Error loading design ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/CHNCTRL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd WARNING:HDLParsers:3215 - Unit work/CHNCTRL/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd line 149: The following signals are missing in the process sensitivity list: rstdataready. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0030> created at line 445. Found 12-bit comparator less for signal <$n0031> created at line 407. Found 12-bit comparator less for signal <$n0032> created at line 445. Found 12-bit comparator greatequal for signal <$n0037> created at line 407. Found 12-bit comparator greatequal for signal <$n0038> created at line 445. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 implementation constraint: INIT=s : cnt_val1_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 69 equations into 8 function blocks.............................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1068. ..... The number of paths traced: 2137. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd line 149: The following signals are missing in the process sensitivity list: rstdataready. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0030> created at line 445. Found 12-bit comparator less for signal <$n0031> created at line 407. Found 12-bit comparator less for signal <$n0032> created at line 445. Found 12-bit comparator greatequal for signal <$n0037> created at line 407. Found 12-bit comparator greatequal for signal <$n0038> created at line 445. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 implementation constraint: INIT=s : cnt_val1_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 69 equations into 8 function blocks.............................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1068. ..... The number of paths traced: 2137. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0030> created at line 445. Found 12-bit comparator less for signal <$n0031> created at line 407. Found 12-bit comparator less for signal <$n0032> created at line 445. Found 12-bit comparator greatequal for signal <$n0037> created at line 407. Found 12-bit comparator greatequal for signal <$n0038> created at line 445. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 implementation constraint: INIT=s : cnt_val1_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 69 equations into 8 function blocks.............................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1068. ..... The number of paths traced: 2137. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0030> created at line 445. Found 12-bit comparator less for signal <$n0031> created at line 407. Found 12-bit comparator less for signal <$n0032> created at line 445. Found 12-bit comparator greatequal for signal <$n0037> created at line 407. Found 12-bit comparator greatequal for signal <$n0038> created at line 445. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 implementation constraint: INIT=s : cnt_val1_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 69 equations into 8 function blocks.............................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/CHNCTRL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd WARNING:HDLParsers:3215 - Unit work/CHNCTRL/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3 is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo3.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2 is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1 is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Final_2004_11_22/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0030> created at line 445. Found 12-bit comparator less for signal <$n0031> created at line 407. Found 12-bit comparator less for signal <$n0032> created at line 445. Found 12-bit comparator greatequal for signal <$n0037> created at line 407. Found 12-bit comparator greatequal for signal <$n0038> created at line 445. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 implementation constraint: INIT=s : cnt_val1_3 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization............... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 69 equations into 8 function blocks.............................. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1070. ..... The number of paths traced: 2141. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0029> created at line 437. Found 12-bit comparator less for signal <$n0030> created at line 405. Found 12-bit comparator less for signal <$n0031> created at line 437. Found 12-bit comparator greatequal for signal <$n0036> created at line 405. Found 12-bit comparator greatequal for signal <$n0037> created at line 437. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 71 equations into 8 function blocks............................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1070. ..... The number of paths traced: 2141. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0028> created at line 435. Found 12-bit comparator less for signal <$n0029> created at line 405. Found 12-bit comparator less for signal <$n0030> created at line 435. Found 12-bit comparator greatequal for signal <$n0035> created at line 405. Found 12-bit comparator greatequal for signal <$n0036> created at line 435. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization.................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... ERROR:Cpld:853 - Insufficient number of product terms. This design needs at least 726 but only 720 left after allocating other resources. Device 95144XL100 was disqualified. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0029> created at line 437. Found 12-bit comparator less for signal <$n0030> created at line 405. Found 12-bit comparator less for signal <$n0031> created at line 437. Found 12-bit comparator greatequal for signal <$n0036> created at line 405. Found 12-bit comparator greatequal for signal <$n0037> created at line 437. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 71 equations into 8 function blocks............................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1070. ..... The number of paths traced: 2141. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 349 # Stopped at chnctrl_tbw.ant line 349 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0011> created at line 160. Found 12-bit comparator greatequal for signal <$n0012> created at line 160. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit adder for signal <$n0029> created at line 437. Found 12-bit comparator less for signal <$n0030> created at line 405. Found 12-bit comparator less for signal <$n0031> created at line 437. Found 12-bit comparator greatequal for signal <$n0036> created at line 405. Found 12-bit comparator greatequal for signal <$n0037> created at line 437. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 12-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 3 12-bit comparator greatequal : 3 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization........... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 71 equations into 8 function blocks............................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1070. ..... The number of paths traced: 2141. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 349 # Stopped at chnctrl_tbw.ant line 349 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. ERROR:HDLParsers:3312 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 169. Undefined symbol 'tmode'. ERROR:HDLParsers:1209 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 169. tmode: Undefined symbol (last report in this block) ERROR:HDLParsers:851 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 165. Formal tmode of fifo3 with no default value must be associated with an actual value. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # ** Error: chnctrl.vhd(169): Unknown identifier: tmode # ** Error: chnctrl.vhd(169): Unknown identifier: tmode # -- Loading entity fifo3 # -- Loading entity trigger_synch # ** Error: chnctrl.vhd(185): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./chnctrl_tbw.ado line 17 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 349 # Stopped at chnctrl_tbw.ant line 349 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 349 # Stopped at chnctrl_tbw.ant line 349 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO3/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1 is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 4 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0012> created at line 163. Found 12-bit comparator greatequal for signal <$n0013> created at line 163. Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0030> created at line 437. Found 12-bit comparator less for signal <$n0031> created at line 405. Found 13-bit comparator less for signal <$n0032> created at line 437. Found 12-bit comparator greatequal for signal <$n0037> created at line 405. Found 13-bit comparator greatequal for signal <$n0038> created at line 437. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 3 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 13-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 2 12-bit comparator greatequal : 2 13-bit comparator less : 1 13-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 37612 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization.......... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 71 equations into 8 function blocks................................................................ Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1104. ...... The number of paths traced: 2209. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. ERROR:HDLParsers:3312 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd Line 191. Undefined symbol 'cnt_ovf2'. ERROR:HDLParsers:1209 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd Line 191. cnt_ovf2: Undefined symbol (last report in this block) tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 4 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0012> created at line 168. Found 12-bit comparator greatequal for signal <$n0013> created at line 168. Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 2 1-bit register : 2 # Counters : 1 12-bit up counter : 1 # Comparators : 2 12-bit comparator less : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 4 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0012> created at line 168. Found 12-bit comparator greatequal for signal <$n0013> created at line 168. Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 436. Found 12-bit comparator less for signal <$n0029> created at line 405. Found 13-bit comparator less for signal <$n0030> created at line 436. Found 12-bit comparator greatequal for signal <$n0035> created at line 405. Found 13-bit comparator greatequal for signal <$n0036> created at line 436. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 13-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 2 12-bit comparator greatequal : 2 13-bit comparator less : 1 13-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Sources are: Inst_fifo2:dataready, Inst_fifo3:dataready ERROR:Xst:415 - Synthesis failed CPU : 25.54 / 26.77 s | Elapsed : 26.00 / 26.00 s --> Total memory usage is 51804 kilobytes Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). ERROR:Xst:762 - E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd line 147: No default binding for component: . Port does not match. --> Total memory usage is 47708 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 433. Found 12-bit comparator less for signal <$n0029> created at line 402. Found 13-bit comparator less for signal <$n0030> created at line 433. Found 12-bit comparator greatequal for signal <$n0035> created at line 402. Found 13-bit comparator greatequal for signal <$n0036> created at line 433. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 3 3-bit register : 1 1-bit register : 2 # Counters : 2 12-bit up counter : 2 # Adders/Subtractors : 2 3-bit adder : 1 13-bit adder : 1 # Comparators : 5 3-bit comparator less : 1 12-bit comparator less : 1 13-bit comparator less : 1 12-bit comparator greatequal : 1 13-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 61. Found 3-bit adder for signal <$n0015> created at line 62. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 4 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0012> created at line 168. Found 12-bit comparator greatequal for signal <$n0013> created at line 168. Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 433. Found 12-bit comparator less for signal <$n0029> created at line 402. Found 13-bit comparator less for signal <$n0030> created at line 433. Found 12-bit comparator greatequal for signal <$n0035> created at line 402. Found 13-bit comparator greatequal for signal <$n0036> created at line 433. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 9 1-bit register : 7 3-bit register : 1 5-bit register : 1 # Counters : 3 12-bit up counter : 3 # Adders/Subtractors : 3 3-bit adder : 1 13-bit adder : 1 5-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 2 12-bit comparator greatequal : 2 13-bit comparator less : 1 13-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... implementation constraint: INIT=s : cnt_8 implementation constraint: INIT=s : cnt_9 implementation constraint: INIT=s : cnt_6 implementation constraint: INIT=s : cnt_7 implementation constraint: INIT=s : cnt_11 implementation constraint: INIT=s : cnt_10 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_3 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_5 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- WARNING:HDLParsers:3215 - Unit work/FIFO1 is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd WARNING:HDLParsers:3215 - Unit work/FIFO1/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo1_tbw # -- Compiling architecture testbench_arch of fifo1_tbw # -- Loading entity fifo1 # -- Compiling configuration fifo1_cfg # -- Loading entity fifo1_tbw # -- Loading architecture testbench_arch of fifo1_tbw # vsim -lib work -t 1ps fifo1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo1_tbw(testbench_arch) # Loading work.fifo1(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 8512 ns Iteration: 0 Process: /fifo1_tbw/line__120 File: fifo1_tbw.ant # Break at fifo1_tbw.ant line 144 # Stopped at fifo1_tbw.ant line 144 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo1_tbw # -- Compiling architecture testbench_arch of fifo1_tbw # -- Loading entity fifo1 # -- Compiling configuration fifo1_cfg # -- Loading entity fifo1_tbw # -- Loading architecture testbench_arch of fifo1_tbw # vsim -lib work -t 1ps fifo1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo1_tbw(testbench_arch) # Loading work.fifo1(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 8512 ns Iteration: 0 Process: /fifo1_tbw/line__120 File: fifo1_tbw.ant # Break at fifo1_tbw.ant line 147 # Stopped at fifo1_tbw.ant line 147 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo1_tbw # -- Compiling architecture testbench_arch of fifo1_tbw # -- Loading entity fifo1 # -- Compiling configuration fifo1_cfg # -- Loading entity fifo1_tbw # -- Loading architecture testbench_arch of fifo1_tbw # vsim -lib work -t 1ps fifo1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo1_tbw(testbench_arch) # Loading work.fifo1(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 10012 ns Iteration: 0 Process: /fifo1_tbw/line__120 File: fifo1_tbw.ant # Break at fifo1_tbw.ant line 147 # Stopped at fifo1_tbw.ant line 147 Project Navigator Auto-Make Log File ------------------------------------- WARNING:HDLParsers:3215 - Unit work/CHNCTRL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd WARNING:HDLParsers:3215 - Unit work/CHNCTRL/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/chnctrl.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo1 # -- Compiling architecture behavioral of fifo1 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fifo1 # -- Loading entity fifo2 # -- Loading entity fifo3 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fifo1(behavioral) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.fifo3(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo3_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo3_tbw # -- Compiling architecture testbench_arch of fifo3_tbw # -- Loading entity fifo3 # -- Compiling configuration fifo3_cfg # -- Loading entity fifo3_tbw # -- Loading architecture testbench_arch of fifo3_tbw # vsim -lib work -t 1ps fifo3_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo3_tbw(testbench_arch) # Loading work.fifo3(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3150 ns Iteration: 0 Process: /fifo3_tbw/line__129 File: fifo3_tbw.ant # Break at fifo3_tbw.ant line 157 # Stopped at fifo3_tbw.ant line 157 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo3_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo3 # -- Compiling architecture behavioral of fifo3 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo3_tbw # -- Compiling architecture testbench_arch of fifo3_tbw # -- Loading entity fifo3 # -- Compiling configuration fifo3_cfg # -- Loading entity fifo3_tbw # -- Loading architecture testbench_arch of fifo3_tbw # vsim -lib work -t 1ps fifo3_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo3_tbw(testbench_arch) # Loading work.fifo3(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3150 ns Iteration: 0 Process: /fifo3_tbw/line__129 File: fifo3_tbw.ant # Break at fifo3_tbw.ant line 157 # Stopped at fifo3_tbw.ant line 157 Project Navigator Auto-Make Log File ------------------------------------- Started process "View RTL Schematic". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/TRIGGER_SYNCH/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/DFFEN/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/dffen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2 is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/FIFO2/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/fifo2.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd in Library work. Architecture behavioral of Entity fifo3 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo3.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 4 | | Outputs | 3 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 12-bit comparator less for signal <$n0012> created at line 168. Found 12-bit comparator greatequal for signal <$n0013> created at line 168. Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 433. Found 12-bit comparator less for signal <$n0029> created at line 402. Found 13-bit comparator less for signal <$n0030> created at line 433. Found 12-bit comparator greatequal for signal <$n0035> created at line 402. Found 13-bit comparator greatequal for signal <$n0036> created at line 433. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0007> created at line 139. Found 5-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 3 # Registers : 8 1-bit register : 7 3-bit register : 1 # Counters : 4 12-bit up counter : 3 5-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 13-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 12-bit comparator less : 2 12-bit comparator greatequal : 2 13-bit comparator less : 1 13-bit comparator greatequal : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_2 ... Encoding for FSM_2 is Gray flip-flop = D Selecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = T Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Completed process "View RTL Schematic". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 435. Found 12-bit comparator less for signal <$n0029> created at line 404. Found 13-bit comparator less for signal <$n0030> created at line 435. Found 12-bit comparator greatequal for signal <$n0035> created at line 404. Found 13-bit comparator greatequal for signal <$n0036> created at line 435. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 3 3-bit register : 1 1-bit register : 2 # Counters : 2 12-bit up counter : 2 # Adders/Subtractors : 2 3-bit adder : 1 13-bit adder : 1 # Comparators : 5 3-bit comparator less : 1 12-bit comparator less : 1 13-bit comparator less : 1 12-bit comparator greatequal : 1 13-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 264 # Stopped at fifo2ctrl_tbw.ant line 264 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fifo2ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fifo2 # -- Compiling architecture behavioral of fifo2 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fifo2ctrl_tbw # -- Compiling architecture testbench_arch of fifo2ctrl_tbw # -- Loading entity fifo2 # -- Compiling configuration fifo2_cfg # -- Loading entity fifo2ctrl_tbw # -- Loading architecture testbench_arch of fifo2ctrl_tbw # vsim -lib work -t 1ps fifo2ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fifo2ctrl_tbw(testbench_arch) # Loading work.fifo2(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 28400 ns Iteration: 0 Process: /fifo2ctrl_tbw/line__201 File: fifo2ctrl_tbw.ant # Break at fifo2ctrl_tbw.ant line 265 # Stopped at fifo2ctrl_tbw.ant line 265 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:800 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 424. Type of ptrg_val_sig is incompatible with type of 5. ERROR:HDLParsers:800 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 427. Type of ptrg_val_sig is incompatible with type of 10. ERROR:HDLParsers:800 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 430. Type of ptrg_val_sig is incompatible with type of 20. ERROR:HDLParsers:800 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 433. Type of ptrg_val_sig is incompatible with type of 25. ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 453. Undefined symbol 'cnt_val1'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 453. cnt_val1: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. Undefined symbol 'cnt_record_pt'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. cnt_record_pt: Undefined symbol (last report in this block) ERROR:HDLParsers:808 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 484. < can not have such operands in this context. ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 453. Undefined symbol 'cnt_val1'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 453. cnt_val1: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. Undefined symbol 'cnt_record_pt'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. cnt_record_pt: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. Undefined symbol 'cnt_record_pt'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 472. cnt_record_pt: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 477. Undefined symbol 'cnt_record_pt'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 494. cnt_record_pt: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3312 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 477. Undefined symbol 'cnt_record_pt'. ERROR:HDLParsers:1209 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 494. cnt_record_pt: Undefined symbol (last report in this block) ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 539. parse error, unexpected PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd, now is E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd, now is E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 150 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 321 # Stopped at fsm1_tbw.ant line 321 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 150 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 321 # Stopped at fsm1_tbw.ant line 321 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 396 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 321 # Stopped at fsm1_tbw.ant line 321 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3312 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 70. Undefined symbol 'fmst'. ERROR:HDLParsers:1209 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 70. fmst: Undefined symbol (last report in this block) ERROR:HDLParsers:507 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 69. std_logic is not a correct resolution function name ERROR:HDLParsers:164 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 70. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 396 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 341 # Stopped at fsm1_tbw.ant line 341 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 396 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 341 # Stopped at fsm1_tbw.ant line 341 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 396 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 341 # Stopped at fsm1_tbw.ant line 341 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 338 # Stopped at fsm1_tbw.ant line 338 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 338 # Stopped at fsm1_tbw.ant line 338 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 338 # Stopped at fsm1_tbw.ant line 338 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__315 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 344 # Stopped at fsm1_tbw.ant line 344 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do ren_wen_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ren_wen_tbw # -- Compiling architecture testbench_arch of ren_wen_tbw # -- Loading entity ren_wen # -- Compiling configuration ren_wen_cfg # -- Loading entity ren_wen_tbw # -- Loading architecture testbench_arch of ren_wen_tbw # vsim -lib work -t 1ps ren_wen_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.ren_wen_tbw(testbench_arch) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3112 ns Iteration: 0 Process: /ren_wen_tbw/line__112 File: ren_wen_tbw.ant # Break at ren_wen_tbw.ant line 152 # Stopped at ren_wen_tbw.ant line 152 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1554 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 381 # Stopped at fsm1_tbw.ant line 381 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 381 # Stopped at fsm1_tbw.ant line 381 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # ** Error: fsm1.vhd(246): near "else": expecting: ';' # ** Error: fsm1.vhd(252): near "when": expecting: END_ # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./fsm1_tbw.ado line 12 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd, automatic determination of correct order of compilation of files in project file fsm1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:164 - E:\Xilinx\ChannelCtrl\Chnctrl/fsm1.vhd Line 246. parse error, unexpected ELSE, expecting SEMICOLON ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:164 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 188. parse error, unexpected CLOSEPAR, expecting IDENTIFIER or STRING_LITERAL ERROR:HDLParsers:164 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 209. parse error, unexpected IF ERROR:HDLParsers:164 - E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd Line 213. parse error, unexpected ELSE ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 6456 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 10956 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 384 # Stopped at fsm1_tbw.ant line 384 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 10956 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 10956 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 10956 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12656 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 16100 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 16100 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 16100 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 16100 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 387 # Stopped at fsm1_tbw.ant line 387 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 16100 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 390 # Stopped at fsm1_tbw.ant line 390 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 18412 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 396 # Stopped at fsm1_tbw.ant line 396 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 411 # Stopped at fsm1_tbw.ant line 411 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 417 # Stopped at fsm1_tbw.ant line 417 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__355 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 417 # Stopped at fsm1_tbw.ant line 417 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/FSM1 is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd WARNING:HDLParsers:3215 - Unit work/FSM1/BEHAVIORAL is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/fsm1.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/REN_WEN/BEHAVIORAL is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/ren_wen.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd WARNING:HDLParsers:3215 - Unit work/DECIM is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd WARNING:HDLParsers:3215 - Unit work/DECIM/BEHAVIORAL is now defined in a different file: was E:/Xilinx/ChannelCtrl/Chnctrl/decim.vhd, now is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd line 564: The following signals are missing in the process sensitivity list: rstdataready. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 8 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- WARNING:Xst:737 - Found 3-bit latch for signal . Found 5-bit comparator less for signal <$n0042> created at line 477. Found 12-bit comparator less for signal <$n0043> created at line 508. Found 12-bit comparator less for signal <$n0044> created at line 511. Found 12-bit comparator less for signal <$n0045> created at line 546. Found 5-bit comparator greatequal for signal <$n0052> created at line 477. Found 12-bit comparator greatequal for signal <$n0053> created at line 511. Found 12-bit comparator greatequal for signal <$n0054> created at line 508. Found 12-bit adder for signal <$n0055> created at line 547. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Latches : 1 3-bit latch : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd line 564: The following signals are missing in the process sensitivity list: rstdataready. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 8 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- WARNING:Xst:737 - Found 3-bit latch for signal . Found 5-bit comparator less for signal <$n0042> created at line 477. Found 12-bit comparator less for signal <$n0043> created at line 508. Found 12-bit comparator less for signal <$n0044> created at line 511. Found 12-bit comparator less for signal <$n0045> created at line 546. Found 5-bit comparator greatequal for signal <$n0052> created at line 477. Found 12-bit comparator greatequal for signal <$n0053> created at line 511. Found 12-bit comparator greatequal for signal <$n0054> created at line 508. Found 12-bit adder for signal <$n0055> created at line 547. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Latches : 1 3-bit latch : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd line 554: The following signals are missing in the process sensitivity list: rstdataready. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 8 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 467. Found 12-bit comparator less for signal <$n0040> created at line 498. Found 12-bit comparator less for signal <$n0041> created at line 501. Found 12-bit comparator less for signal <$n0042> created at line 536. Found 5-bit comparator greatequal for signal <$n0048> created at line 467. Found 12-bit comparator greatequal for signal <$n0049> created at line 501. Found 12-bit comparator greatequal for signal <$n0050> created at line 498. Found 12-bit adder for signal <$n0051> created at line 537. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 8 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 467. Found 12-bit comparator less for signal <$n0040> created at line 498. Found 12-bit comparator less for signal <$n0041> created at line 501. Found 12-bit comparator less for signal <$n0042> created at line 536. Found 5-bit comparator greatequal for signal <$n0048> created at line 467. Found 12-bit comparator greatequal for signal <$n0049> created at line 501. Found 12-bit comparator greatequal for signal <$n0050> created at line 498. Found 12-bit adder for signal <$n0051> created at line 537. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 357 # Stopped at fsm1_tbw.ant line 357 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 8 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 468. Found 12-bit comparator less for signal <$n0040> created at line 499. Found 12-bit comparator less for signal <$n0041> created at line 502. Found 12-bit comparator less for signal <$n0042> created at line 537. Found 5-bit comparator greatequal for signal <$n0048> created at line 468. Found 12-bit comparator greatequal for signal <$n0049> created at line 502. Found 12-bit comparator greatequal for signal <$n0050> created at line 499. Found 12-bit adder for signal <$n0051> created at line 538. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:1401 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 295. Object dataready of mode OUT can not be read. --> Total memory usage is 44704 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 482. Found 12-bit comparator less for signal <$n0040> created at line 513. Found 12-bit comparator less for signal <$n0041> created at line 516. Found 12-bit comparator less for signal <$n0042> created at line 551. Found 5-bit comparator greatequal for signal <$n0048> created at line 482. Found 12-bit comparator greatequal for signal <$n0049> created at line 516. Found 12-bit comparator greatequal for signal <$n0050> created at line 513. Found 12-bit adder for signal <$n0051> created at line 552. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 357 # Stopped at fsm1_tbw.ant line 357 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 363 # Stopped at fsm1_tbw.ant line 363 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 372 # Stopped at fsm1_tbw.ant line 372 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 118. Undefined symbol 'ptrig_data'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 118. ptrig_data: Undefined symbol (last report in this block) ERROR:HDLParsers:851 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd Line 111. Formal ptrig_data of fsm1 with no default value must be associated with an actual value. --> Total memory usage is 44704 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 482. Found 12-bit comparator less for signal <$n0040> created at line 513. Found 12-bit comparator less for signal <$n0041> created at line 516. Found 12-bit comparator less for signal <$n0042> created at line 551. Found 5-bit comparator greatequal for signal <$n0048> created at line 482. Found 12-bit comparator greatequal for signal <$n0049> created at line 516. Found 12-bit comparator greatequal for signal <$n0050> created at line 513. Found 12-bit adder for signal <$n0051> created at line 552. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 482. Found 12-bit comparator less for signal <$n0040> created at line 513. Found 12-bit comparator less for signal <$n0041> created at line 516. Found 12-bit comparator less for signal <$n0042> created at line 551. Found 5-bit comparator greatequal for signal <$n0048> created at line 482. Found 12-bit comparator greatequal for signal <$n0049> created at line 516. Found 12-bit comparator greatequal for signal <$n0050> created at line 513. Found 12-bit adder for signal <$n0051> created at line 552. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... ERROR:NgdBuild:755 - Line 17 in 'chnctrl.ucf': Could not find net(s) 'ptrg_data<0>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 18 in 'chnctrl.ucf': Could not find net(s) 'ptrg_data<1>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "chnctrl.ucf". Writing NGDBUILD log file "chnctrl.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization..................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 55 equations into 8 function blocks....... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........ The number of paths traced: 612. ... The number of paths traced: 1225. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 352 # Stopped at chnctrl_tbw.ant line 352 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 38940 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 352 # Stopped at chnctrl_tbw.ant line 352 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 40182 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 372 # Stopped at fsm1_tbw.ant line 372 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 372 # Stopped at fsm1_tbw.ant line 372 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:3370 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 473. Value 511 is not included in the range, 31 downto 0, of ptrg_val_sig. ERROR:HDLParsers:3370 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 476. Value 1023 is not included in the range, 31 downto 0, of ptrg_val_sig. ERROR:HDLParsers:3370 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 479. Value 2047 is not included in the range, 31 downto 0, of ptrg_val_sig. ERROR:HDLParsers:3370 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 482. Value 2559 is not included in the range, 31 downto 0, of ptrg_val_sig. --> Total memory usage is 44704 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 537. Found 12-bit comparator less for signal <$n0041> created at line 540. Found 12-bit comparator less for signal <$n0042> created at line 575. Found 5-bit comparator greatequal for signal <$n0048> created at line 502. Found 12-bit comparator greatequal for signal <$n0049> created at line 540. Found 12-bit comparator greatequal for signal <$n0050> created at line 537. Found 12-bit adder for signal <$n0051> created at line 576. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization........................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 56 equations into 8 function blocks................ Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 825. .... The number of paths traced: 1651. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 40182 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 40182 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 346 # Stopped at chnctrl_tbw.ant line 346 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 40182 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 340 # Stopped at chnctrl_tbw.ant line 340 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 40182 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 56151 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 73851 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 78591 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 87951 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 537. Found 12-bit comparator less for signal <$n0041> created at line 540. Found 12-bit comparator less for signal <$n0042> created at line 575. Found 5-bit comparator greatequal for signal <$n0048> created at line 502. Found 12-bit comparator greatequal for signal <$n0049> created at line 540. Found 12-bit comparator greatequal for signal <$n0050> created at line 537. Found 12-bit adder for signal <$n0051> created at line 576. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization........................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 56 equations into 8 function blocks............. Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 837. .... The number of paths traced: 1675. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 293156 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd Line 546. parse error, unexpected PROCESS, expecting IF --> Total memory usage is 44704 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0041> created at line 536. Found 12-bit comparator less for signal <$n0042> created at line 561. Found 12-bit comparator less for signal <$n0043> created at line 586. Found 5-bit comparator greatequal for signal <$n0049> created at line 502. Found 12-bit comparator greatequal for signal <$n0050> created at line 536. Found 12-bit adder for signal <$n0051> created at line 587. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 561. Found 12-bit comparator less for signal <$n0042> created at line 586. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 587. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 372 # Stopped at fsm1_tbw.ant line 372 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 375 # Stopped at fsm1_tbw.ant line 375 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 561. Found 12-bit comparator less for signal <$n0042> created at line 586. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 587. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization..................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 55 equations into 8 function blocks...................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........ The number of paths traced: 691. ... The number of paths traced: 1383. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization..................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 55 equations into 8 function blocks............... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........ The number of paths traced: 622. ... The number of paths traced: 1245. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization..................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 55 equations into 8 function blocks............... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........ The number of paths traced: 622. ... The number of paths traced: 1245. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 293156 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do fsm1_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity fsm1_tbw # -- Compiling architecture testbench_arch of fsm1_tbw # -- Loading entity fsm1 # -- Compiling configuration fsm1_cfg # -- Loading entity fsm1_tbw # -- Loading architecture testbench_arch of fsm1_tbw # vsim -lib work -t 1ps fsm1_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.fsm1_tbw(testbench_arch) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 35656 ns Iteration: 0 Process: /fsm1_tbw/line__295 File: fsm1_tbw.ant # Break at fsm1_tbw.ant line 372 # Stopped at fsm1_tbw.ant line 372 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 9 1-bit register : 7 3-bit register : 1 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 293156 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 435356 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 497512 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 497512 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 497512 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do chnctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity decim # -- Compiling architecture behavioral of decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ren_wen # -- Compiling architecture behavioral of ren_wen # -- Loading entity decim # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity fsm1 # -- Compiling architecture behavioral of fsm1 # -- Loading entity ren_wen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dffen # -- Compiling architecture behavioral of dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity trigger_synch # -- Compiling architecture behavioral of trigger_synch # -- Loading entity dffen # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity chnctrl # -- Compiling architecture behavioral of chnctrl # -- Loading entity fsm1 # -- Loading entity trigger_synch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity chnctrl_tbw # -- Compiling architecture testbench_arch of chnctrl_tbw # -- Loading entity chnctrl # -- Compiling configuration chnctrl_cfg # -- Loading entity chnctrl_tbw # -- Loading architecture testbench_arch of chnctrl_tbw # vsim -lib work -t 1ps chnctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.chnctrl_tbw(testbench_arch) # Loading work.chnctrl(behavioral) # Loading work.fsm1(behavioral) # Loading work.ren_wen(behavioral) # Loading work.decim(behavioral) # Loading work.trigger_synch(behavioral) # Loading work.dffen(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 497512 ns Iteration: 0 Process: /chnctrl_tbw/line__298 File: chnctrl_tbw.ant # Break at chnctrl_tbw.ant line 343 # Stopped at chnctrl_tbw.ant line 343 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Unable to checkout a license. Vsim is closing. ** Fatal: Invalid license environment. Application closing. ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Architecture behavioral of Entity fsm1 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 26 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 513. Found 12-bit comparator less for signal <$n0040> created at line 547. Found 12-bit comparator less for signal <$n0041> created at line 576. Found 12-bit comparator less for signal <$n0042> created at line 601. Found 5-bit comparator greatequal for signal <$n0047> created at line 513. Found 12-bit comparator greatequal for signal <$n0048> created at line 547. Found 12-bit comparator greatequal for signal <$n0049> created at line 601. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 Counter(s). inferred 5 D-type flip-flop(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 8 1-bit register : 7 3-bit register : 1 # Counters : 3 5-bit up counter : 1 12-bit up counter : 2 # Adders/Subtractors : 1 3-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35632 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization...................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 54 equations into 8 function blocks................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 812. .... The number of paths traced: 1625. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 26 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 513. Found 12-bit comparator less for signal <$n0040> created at line 547. Found 12-bit comparator less for signal <$n0041> created at line 576. Found 12-bit comparator less for signal <$n0042> created at line 601. Found 5-bit comparator greatequal for signal <$n0047> created at line 513. Found 12-bit comparator greatequal for signal <$n0048> created at line 547. Found 12-bit comparator greatequal for signal <$n0049> created at line 601. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 Counter(s). inferred 5 D-type flip-flop(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 8 1-bit register : 7 3-bit register : 1 # Counters : 3 5-bit up counter : 1 12-bit up counter : 2 # Adders/Subtractors : 1 3-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35596 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization...................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 54 equations into 8 function blocks................... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 812. .... The number of paths traced: 1625. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 26 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 521. Found 12-bit comparator less for signal <$n0040> created at line 555. Found 12-bit comparator less for signal <$n0041> created at line 584. Found 12-bit comparator less for signal <$n0042> created at line 609. Found 5-bit comparator greatequal for signal <$n0047> created at line 521. Found 12-bit comparator greatequal for signal <$n0048> created at line 555. Found 12-bit comparator greatequal for signal <$n0049> created at line 609. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 Counter(s). inferred 4 D-type flip-flop(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 8 1-bit register : 7 3-bit register : 1 # Counters : 3 5-bit up counter : 1 12-bit up counter : 2 # Adders/Subtractors : 1 3-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35596 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization...................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 53 equations into 8 function blocks........... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 812. .... The number of paths traced: 1625. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd in Library work. Architecture behavioral of Entity dffen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd in Library work. Architecture behavioral of Entity trigger_synch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd in Library work. Architecture behavioral of Entity chnctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/dffen.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/trigger_synch.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 26 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 525. Found 12-bit comparator less for signal <$n0040> created at line 559. Found 12-bit comparator less for signal <$n0041> created at line 588. Found 12-bit comparator less for signal <$n0042> created at line 613. Found 5-bit comparator greatequal for signal <$n0047> created at line 525. Found 12-bit comparator greatequal for signal <$n0048> created at line 559. Found 12-bit comparator greatequal for signal <$n0049> created at line 613. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 3 Counter(s). inferred 4 D-type flip-flop(s). inferred 7 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 8 1-bit register : 7 3-bit register : 1 # Counters : 3 5-bit up counter : 1 12-bit up counter : 2 # Adders/Subtractors : 1 3-bit adder : 1 # Comparators : 8 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_5 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=s : cnt_transfer_0 implementation constraint: INIT=s : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=s : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=s : cnt_record_0 implementation constraint: INIT=s : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=s : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc chnctrl.ucf -p xc9500xl chnctrl.ngc chnctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/chnctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "chnctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35596 kilobytes Writing NGD file "chnctrl.ngd" ... Writing NGDBUILD log file "chnctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization......... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 54 equations into 8 function blocks........... Design chnctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 825. .... The number of paths traced: 1651. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock trigger ... Cycle time table for clock clk ... chnctrl.tim has been created. Generating Stamp model files chnctrl.mod, chnctrl.data ... chnctrl.mod has been created. chnctrl.data has been created. Completed process "Generate Timing".