library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dffen is
    Port ( reset 	: in std_logic;
           clk 	: in std_logic;
           en 		: in std_logic;
           din 	: in std_logic;
           qout 	: out std_logic);
end dffen;

architecture Behavioral of dffen is

-- signals
signal q : std_logic;

begin

	qout <= q;

	process (reset, clk, en, din)
	begin
		
		if reset = '0' then 
			q <= '0';

		elsif (clk'event and clk = '1') then

			if en = '0' then
				q <= din;
			else
				q <= q;
			end if;
		
		end if;
	
	end process;

end Behavioral;
