library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.1 / February 25 2004 
-- 
--
-- ********************************************

entity fifo1 is
    Port ( reset 	: in std_logic;
           clk 	: in std_logic;
           acqen : in std_logic;
           rst1 	: out std_logic;
           wen1 	: out std_logic;
           ren1 	: out std_logic);
end fifo1;

architecture Behavioral of fifo1 is
 
-- signals
-------------------------------------------------------
	type state_TYPE is (s0, s1, s2);
	attribute ENUM_ENCODING: STRING;
	attribute ENUM_ENCODING of state_TYPE: type is "00 01 10";

	signal state, next_state : state_TYPE;

	signal delay			: std_logic;
	signal cnt_en 			: std_logic;
	signal cnt				: integer range 31 downto 0;

-------------------------------------------------------
-- architecture description
-------------------------------------------------------
begin


	-- processes
	----------------------------------------------------

	-- FSM sequence / definition	
	process (reset, clk)
	begin
		if reset = '0' then
			state <= s0;
		elsif (clk'event and clk= '1') then
				state <= next_state;
			else
				state <= state;
		end if;
	end process;
  
	
	-- FSM Description
	process (state, acqen, delay)
	begin
		case state is

			when s0 =>

				rst1 		<= '0';
				wen1 		<= '1';
				ren1 		<= '1';
				cnt_en	<= '1';

				if acqen = '0' then
					next_state <= s1;
				else
					next_state <= s0;
				end if;
				

			when s1 =>	-- Write is acqend

				rst1 		<= '1';
				wen1 		<= '0';
				ren1 		<= '1';
				cnt_en	<= '0';

				if acqen = '0' then
					if delay = '0' then
						next_state <= s2;
					else
						next_state <= s1;
					end if;
				else
					next_state <= s0;
				end if;


			when s2 =>	-- Write and Read are acqend
							-- Fixed number of samples in FIFO1

				rst1		<= '1';
				wen1 		<= '0';
				ren1 		<= '0';
				cnt_en	<= '1';

				if acqen = '0' then
					next_state <= s2;
				else
					next_state <= s0;
				end if;


 			when others =>

				rst1		<= '0';
				wen1 		<= '1';
				ren1 		<= '1';
				cnt_en	<= '1';
			
				next_state <= s0;

		end case;
    end process;

	-- Counter / Delay
	process (clk, cnt_en)
	begin
		if cnt_en = '1' then

			cnt <= 0;
			delay <= '1';

		elsif (clk'event and clk = '1') then

			if cnt < 30 then
				cnt <= cnt + 1;
				delay <= '1';
			else
				cnt <= cnt; 
				delay <= '0';
			end if;

		end if;
    end process;

end Behavioral;

