library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--  library UNISIM;
--  use UNISIM.VComponents.all;


-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- REV 1.1 / February 25 2004 
-- 
--
-- ********************************************
-- ************************************************************************
-- REV 1.3 / June 2006
-- Major revision !
-- (a)consolidation of fifo1,2,3 codes into a single fsm
-- (b)Change in the data transfer to fifo3:
-- (b-1)	In acq with trigger, the transfer takes place after
-- 		the record has been stored in fifo2.  The acquisition
--			is halted (no write in fifo2) until transfer completed.
--	(b-2)	In acq w/o trigger, the fifo are transparent and the data ready
--			is generated once the record length is fifo3 is 4086 (4096-10).
-- ************************************************************************

-- ##################################################################### --
-- TRIGGER MODE																			 --
-- trigmode 																				 --
-- 	0: Acquisition WITH trigger													 --
-- 	1: Acquisition WITHOUT trigger												 --
-- ##################################################################### --

-- ##################################################################### --
-- DECIMATION RATIO																		 --
-- The decimation is performed by controlling the write and read enable. --
-- The clock signals are NOT gated.													 --
--	decim_ratio:																			 --
--		00 <=>  No decimation															 --
--		01 <=>  1:2          															 --
--		10 <=>  1:4																			 --
--		11 <=>  1:8																			 --
--	Once the decim flag (trigger received) is active then the decimation	 --
-- stops																						 --
-- ##################################################################### --

-- ##################################################################### --
-- Pretrigger Data Record Length														 --
-- ptrig_data																				 --
-- 	00:	 512																			 --
--		01:	1024																			 --
--		10:	2048																			 --
--		11:	2560																			 --
-- ##################################################################### --

			  

entity chnctrl is
    Port ( reset 			: in std_logic;
           clk 			: in std_logic;
			  trigmode		: in std_logic;
			  decim_ratio	: in std_logic_vector (1 downto 0);
			  ptrig_data	: in std_logic_vector (1 downto 0);
			  acqen 			: in std_logic;
			  trigger		: in std_logic;
			  rstdataready	: in std_logic; -- rstdtry
			  full3			: in std_logic;

           rst1 			: out std_logic;
           wen1 			: out std_logic;
           ren1 			: out std_logic;
           rst2 			: out std_logic;
           wen2 			: out std_logic;
           ren2 			: out std_logic;
           rst3 			: out std_logic;
           wen3 			: out std_logic;
			  latchtrig		: out std_logic;
			  dflag			: out std_logic;
           dataready 	: out std_logic  -- dtry
          );
end chnctrl;

architecture Behavioral of chnctrl is

	----------------------------------------------------
	-- Definition of Components
	----------------------------------------------------
	COMPONENT fsm1
	PORT(
		reset 			: IN std_logic;
		clk 				: IN std_logic;
		acqen 			: IN std_logic;
		trigmode 		: IN std_logic;
		trigger 			: IN std_logic;
		decim_ratio 	: IN std_logic_vector(1 downto 0);
		ptrig_data 		: IN std_logic_vector(1 downto 0);
		rstdataready 	: IN std_logic;          
		rst1 				: OUT std_logic;
		wen1 				: OUT std_logic;
		ren1 				: OUT std_logic;
		rst2 				: OUT std_logic;
		wen2 				: OUT std_logic;
		ren2 				: OUT std_logic;
		rst3 				: OUT std_logic;
		wen3 				: OUT std_logic;
		trigger_en 		: OUT std_logic;
		decim_flag 		: OUT std_logic;
		dataready 		: OUT std_logic
		);
	END COMPONENT;
--
	COMPONENT trigger_synch
	PORT(
		reset 			: IN std_logic;
		clk 				: IN std_logic;
		trigger_in 		: IN std_logic;
		trigger_en 		: IN std_logic;          
		trigger_out 	: OUT std_logic
		);
	END COMPONENT;

	----------------------------------------------------
	-- Signals
	----------------------------------------------------
	signal acqen_sig 	: std_logic;
	signal trigger_en : std_logic;
	signal trigger_out: std_logic;
	signal reset_trig	: std_logic;
	
	
----------------------------------------------------
-- Architecture Description
----------------------------------------------------

begin
	--	assignments
	acqen_sig	<= acqen or ( not(full3) );
	latchtrig 	<= trigger_en;
	reset_trig 	<= reset and rstdataready;

	--	instances
	-----------------------------
	Inst_fsm1: fsm1 PORT MAP(
		reset 			=> reset,
		clk 				=> clk,
		acqen 			=> acqen_sig,
		trigmode 		=> trigmode,
		trigger 			=> trigger_out,
		decim_ratio 	=> decim_ratio,
		ptrig_data 		=> ptrig_data,
		rstdataready 	=> rstdataready,
		rst1 				=> rst1,
		wen1 				=> wen1,
		ren1 				=> ren1,
		rst2 				=> rst2,
		wen2 				=> wen2,
		ren2 				=> ren2,
		rst3 				=> rst3,
		wen3 				=> wen3,
		trigger_en 		=> trigger_en,
		decim_flag 		=> dflag,
		dataready 		=> dataready
	);

	-----------------------------
	Inst_trigger_synch: trigger_synch PORT MAP(
		reset 			=> reset_trig,
		clk 				=> clk,
		trigger_in 		=> trigger,
		trigger_en 		=> trigger_en,
		trigger_out 	=> trigger_out
	);
	-----------------------------
	
end Behavioral;