library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ren_wen is
    Port ( reset				: in std_logic;
	        clk 				: in std_logic;
           decim_ratio 		: in std_logic_vector (1 downto 0);
			  decim_en			: in std_logic;								-- enable
			  decim_flag		: in std_logic;								-- equivalent to synch'd trigger
           enable_r 			: in std_logic;								-- enable read operation from fifo2 FSM
           enable_w 			: in std_logic;								-- enable write operation from fifo2 FSM 
           wen2 				: out std_logic;								-- wen fifo2
           ren2 				: out std_logic);								-- ren fifo2
end ren_wen;




architecture Behavioral of ren_wen is

	-- components
	COMPONENT decim
	PORT(
		reset 		: IN std_logic;
		clk 			: IN std_logic;
		decim_ratio : IN std_logic_vector(1 downto 0);	  -- decim ratio
		decim_en 	: IN std_logic;							  -- decim enable
		decim_flag 	: IN std_logic;          				  -- decim flag
		decim_sig 	: OUT std_logic							  -- decim signal
		);
	END COMPONENT;


	-- signals
	signal decim_sig	: std_logic;


begin

	-- instanciation
	Inst_decim: decim PORT MAP(
		reset 		=> reset,
		clk 			=> clk,
		decim_ratio => decim_ratio,
		decim_en 	=> decim_en,
		decim_flag 	=> decim_flag,
		decim_sig 	=> decim_sig
	);

	-- process
	process (enable_r, enable_w, decim_sig)
	begin
			
			if enable_w = '0' then
				wen2 <= decim_sig;
			else
				wen2 <= '1';
			end if;

			if enable_r = '0' then
				ren2 <= decim_sig;
			else
				ren2 <= '1';
			end if;
		
	end process;
end Behavioral;
