-- 16-bit register with synchronous load
-- and ansynchronous clear
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity REG16_LC is port (
	DIN 	: in std_logic_vector(15 downto 0);
	LOAD 	: in std_logic;
	CLOCK 	: in std_logic;
	RESET 	: in std_logic;
	DOUT 	: out std_logic_vector(15 downto 0)
); end REG16_LC;

architecture Behavioral of REG16_LC is

signal DOUTsig : std_logic_vector(15 downto 0);

begin	

DOUT <= DOUTsig;

latchproc : process(CLOCK, RESET, LOAD, DIN)
begin
	if RESET = '1' then
		DOUTsig <= (others => '0');
	elsif (CLOCK'event and CLOCK = '1') then
		if (LOAD = '1') then
			DOUTsig <= DIN;
		end if;
	end if;
end process;

end Behavioral;