/*
 *   DIO.h
 * 
 *   Header for the low-level functions communicating with the
 *   hardware.
 *
 *   MARTest image acquisition software
 *   This software has been written to acquire electron microscope
 *   images using the MARTest IC and a DAQ system based on a 
 *   custom FPGA (Xilinx Spartan XC2S15) board, an ADC board (UXO
 *   project - 14-bit 65MHz Analog Device ADC) and a DIO-32HS
 *   board from National Instruments.
 *
 *   (C) 2005-2007, Jean-Marie Bussat - jmbussat@lbl.gov
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#define BOARD_ID 	1	/* From the MAX utility            */
#define CTRL_PORT	2   /* Port used for control functions */
#define DONE		0   /* Done signal (input) is bit 0    */
#define START 		1   /* Start signal (output) is bit 1  */
#define CLR			2   /* Clear signal (output) is bit 2  */
#define A0			3	/* address bit 0 for timing reg.   */
#define A1			4   /* address bit 1 for timing reg.   */
#define A2			5   /* address bit 1 for timing reg.   */
#define REG_INC		6   /* increment register              */
#define REG_DEC     7   /* decrement register              */

#define ADC_PORT	3	/* Port D used to control ADC/FIFO */
/* Port D outputs                                          */
#define REG_RES		0   /* reset timing register           */
#define REG_WEN     1   /* write enable for timing reg.    */
#define RENBA		6   /* FIFO 2 read enable              */
#define RENBB		7   /* FIFO 3 read enable              */


int DIORead( i16 *data);
void PulseResetFIFO(void);
void DoResetFIFO(void);			
void DoneResetFIFO(void);
void EnableFIFOwrite(void);
void DisableFIFOwrite(void);
void SetFIFOreadClock(void);
void ClearFIFOreadClock(void);
void FIFOselect(int chan);
int isEmpty(void);
void TimeRegInc(void);
void TimeRegDec(void);
void TimeRegRes(void);
void TimeReg_SetAddress(int addr);
void TimeRegEn(void);
void TimeRegDis(void);