------------------------------------------------------------------------------ ATLAS SiROD Router FPGA Revision History ------------------------------------------------------------------------------ Version = 3.3f Oct 30, 2015 Changes: Added Data Path pipeline to improve Xoff Handling ------------------------------------------------------------------------------ Version = 3.2f Oct 24, 2015 Changes: Fixed Manual Xoff bug. Register Forced Xoff will now show in the latched status register. ------------------------------------------------------------------------------ Version = 3.1f Aug 3, 2015 Changes: Added Event Over Threshold Counter in Registers 0x004025A0 & 0x004025A4 EOT Count is a 32 bit counter - ADDR A0 is the MSHW and A4 is the LSHW The threshold limit is set in the lower 16 bits of EFB register 0x00402214 ------------------------------------------------------------------------------ Version = 3.0f Mar 12, 2015 Changes: Added manaual Xoff control to register 0x00402500, bit 15 to allow test stand control of Xoff for diagnostics. If bit 15 is logic 1, Xoff is asserted, if bit 15 is logic 0, Xoff is cleared. ------------------------------------------------------------------------------ Version = 2.Ef 11 Jan 2012 Changes: Added S-Link Bandwidth Counters to allow monitoring the overall percentage of time that the Slink is transmitting data to the ROS. Control 0x00402510 Bits[5:4] => Value 0x20 == Count Reset Value 0x10 == Enable Word Count Status 0x00402520 == slink_clk_count[31:16] Status 0x00402524 == slink_clk_count[15:0] Status 0x00402528 == slink_word_count[31:16] Status 0x0040252C == slink_word_count[15:0] The clock counter will turn over to 0 automatically, so the DSP or host must send a periodic reset to prevent an invalid ratio of words to clks Since the counters are 32 bits, the clock counter will cycle through 0 every 107 seconds. ------------------------------------------------------------------------------ Version = 2.Df 27 May 2010 Changes: Added Error Event trapping function. Setup by setting bit 8 in the Trap Command registers to value = '1'. Trps all Error events that pass through the Router. ------------------------------------------------------------------------------ Version = 2.Cf 02 Mar 2010 Changes: Reduced the trap FIFO almost full flag limit from 3 frames to 2 to fix the v2.Bf introduced calibration event data loss issue. ------------------------------------------------------------------------------ Version = 2.Bf 01 Mar 2010 Changes: Fixed the FIFO full/data lost function that was not working because of changes made specifically for the calibration issues that were not carried through to all points in the design. Changes include a new distribution of the word count net to all of the trapping blocks and to the readout register block and asserting the fifo full flag 1 count earlier than in the previous versions. ------------------------------------------------------------------------------ Version = 2.Af 22 Oct 2009 Changes: Removed DSP Masked Link from Byte Stream for Pixel ROD only ------------------------------------------------------------------------------ Version = 2.9f 19 Jan 2009 Changes: Fixed a potential bug by removing a masking bit for the DSP channel almost full flag output. ------------------------------------------------------------------------------ Version = 2.8f 19 Jan 2009 Changes: Added a mask bit to prevent the trap FIFOs from issuing an INT4 interrupt when the MDSP forces one. The mask is enabled when a non-zero value is written to the diagnostic INT4 register in the Router. This is used primarily when the Router is trapping data in the data mode to transfera partially full frame to the SDSP. The FIFO should be flushed after the data transfer is complete. ------------------------------------------------------------------------------ Version = 2.7f 19 Jan 2009 Changes: Added a register to allow user to set the length of time to hold off events between the EFB and the Router in calibration mode only. The new Router register is at 0x0040251C and the default value is 0x8 (200ns). Each counter in the register will increase the delay by 25ns. The delay is used to guarantee that 2 events cannot be in the SL data pipeline simulataneously. This function is disabled in data taking mode. ------------------------------------------------------------------------------ Version = 2.6f 18 Jan 2009 Changes: Added logic to mask trap FIFO almost full when the trap is off. Without the mask bit, the almost full flag from one trap was able to halt the data pipeline when it was off. Reduced the Int4 one shot pulse width to 500ns. ------------------------------------------------------------------------------ Version = 2.5f Changes: Modified the Int4 one shot pulse to last for 1 us when enabled. ------------------------------------------------------------------------------ Version = 2.4f Changes: Reverted Int4 signal to the implementation in version 2.2F. ------------------------------------------------------------------------------ Version = 2.3f Changes: Experimental version that clears Trap Status bit for each event. Changed the Int4 signal to a latched high or low ------------------------------------------------------------------------------ Version = 2.2f Changes: Modified the forced dsp_int4 function to provide a 100ns one shot pulse to force a trap data transfer if the last frame is not full. After forcing a trap data xfer interrupt, the RTR Trap FIFO must be flushed to reset the addr pointers before trying to trap more data. ----------------------------------------------------------------------------- Version = 2.1f Changes: Added Error trapping to the SDSP data trapping. To enable, set bit 7 in RTR_TRAP_CMND_0. The EFB sends a bit in the first word of the event header that indicates that there is an error in the event. All errors are trapped, there is no provision to trap on a specific type of error. ------------------------------------------------------------------------------ Version = 2.0f Changes: Added signal to DSP Data Fifo block to select how AFull is controlled. If the trap is filling in Event driven mode, then AFull is asserted when the trap starts writing to block 3. In Data driven mode, AFull is asserted when the FIFO is 16 words from Full. ------------------------------------------------------------------------------ Version = 1.Ff Changes: Modified Trap FIFO Almost Full algorithm to assert AFull when trap starts filling the 3rd block of the memory structure. ------------------------------------------------------------------------------ Version = 1.Ef Changes: Modified Trap FIFO Almost Full algorithm to fix bug when 4 blocks are occupied. AF now asserted when FIFO is full. ------------------------------------------------------------------------------ Version = 1.Df Changes: Converted Register Block text to Hex format ------------------------------------------------------------------------------ Version = 1.Cf Changes: Built using ISE82i SP3 ------------------------------------------------------------------------------ Version = 1.Cf Changes: Same VHDL as Ver 1.Bf. Built with ISE8.2i SP3 ------------------------------------------------------------------------------ Version = 1.Bf Changes: B0F bug fix ==> Added Hold Next Event Output signal that allows the S-Link Pipeline FIFO to empty the current event before allowing the next event to transmit from the EFB. This function is only active during Calibration Mode (if Cal Back Pressure is set active). The signal is connected using rtr_spare_pin(13) to efb_spare_pin(23). ------------------------------------------------------------------------------ Version = 1.Af Changes: B0F bug fix ==> TBD Increased value for Trap FIFO Almost Full Flag test from 3 blocks to 3 blocks and 192 words. Could cause trouble if all modules are in one group. ------------------------------------------------------------------------------ Version = 1.9F Changes: Modified event_ok detect process to check the event count in the event fragment event count status word. This was the logic used in the RevE code. Removed Error Event Specific trapping until B0F bug is resolved. Error Event trapping is not a specified ROD requirement. ------------------------------------------------------------------------------ Version = 1.8F Changes: Tweaked Trap Event Data block to fix low level bugs in Trap0 and Trap1 ------------------------------------------------------------------------------ Version = 1.7F Changes: Changed S-Link WR Enable masking logic to suppress all S-Link data when it is set to value = 1. Changed Error format header to include number of header words. If 3rd Frag word = 0x00000006 then Error Event Format If 3rd Frag word = 0x00000009 then Normal Event Format ------------------------------------------------------------------------------ Version = 1.6F Changes: Added logic to clear trap registers when TrapReset is active. ------------------------------------------------------------------------------ Version = 1.5F Changes: Masked SLink FF and LDown when Slink WR inhibit is active ------------------------------------------------------------------------------ Version = 1.4F Changes: Trap FIFO loses B0F word in events that are stacked and only fill the first few buffer locations of the last frame. Added latch to trap FIFO Full bit. Pause Event data pipeline by 1 clock anytime the end of block word is written to the trap FIFO. ------------------------------------------------------------------------------ Version = 1.3F Changes: Modified Trap FIFO almost full flag. Asserted at start of last available block. Fixed DSP trap FIFO back pressure bug. SDSP almost full is now routed to WOLH block and the event data pipeline FIFO. Removed latched AFull signal from event data. ------------------------------------------------------------------------------ Version = 1.2F Changes: Fixed HW Capture signal bug in ROL test block mode ------------------------------------------------------------------------------ Version = 1.1F Changes: Added 1 clock to through path Added detection of ROL Test Block to bit17 of "BOF" word 1/24/02 JMJ Increased drive of DSP data drivers from 6 to 12 mA 6/13/00 JMJ Added comment text to describe functions and formats 3/07/00 JMJ Added dspn_sbsram_me_n signals to PORT entity 1/17/00 MLN First version