------------------------------------------------------------------------------ Atlas SiROD SCT Formatter FPGA Revision History ------------------------------------------------------------------------------ Version = 5.4-4F Version Names: fmt_s54-40f.bin Changes: Removed Toxic Link detection logic from prior release. Added an exit case to the Link Decoder for the "Raw Data" state - exits on a Trailer, and can cause the link to send multiple raw data events. Changed trailer generated in Raw Data mode from "0x4400" to 0x"4600". Included FE Simulator into the FPGA Build. Logic uses 99% of the FPGA with the Simulator included. ------------------------------------------------------------------------------ Version = 5.3-0F Version Names: fmt_s53-0f.bin Changes: Added FE Sim module (will remove when more FPGA space is required). FE Pipeline Error test still out(temporarily). Added a Duplicate Chip & Channel Counter to the Link Decoder. If the number of consecutive Chip & Channel values returned from the FE Module is greater than or equal to 16, the "Toxic Link Detected" bit a set and the link decoder state machine goes to a "Wait for Trailer" state. Counting to 16 was chosen arbitrarily, and in future version we will try to minimize the count to save space in the FPGA, but function correctly for all data cases. ------------------------------------------------------------------------------ Version = 5.2-FF Version Names: fmt_s52-Ff.bin Changes: Removed FE Sim module & FE Pipeline Error test (temporarily). Removed "Toxic Link" detection. Added correct functionality for Diagnostic FIFO Trigger and Readout ------------------------------------------------------------------------------ Version = 5.2-CF Version Names: fmt_s52-Cf.bin Changes: Removed FE Sim module. Added function to handle "Toxic Links" in the Detector. Ones that start sending normal data, but then devolve into a never ending stream of "New Clusters" all with identical Chip & Channel code. When the "TL" condition is detected 7 consecutive times on a link, the Link decoder state machine moves into a "Hold Link Off" state, sends an "Event Truncated" trailer, and will not return to the data stream until manually reset by the SCT DAQ Modified the Link Diagnostic FIFOs to capture input data streams on a SW trigger in addition to an L1A. Fixed SW WR_STRB function on for Diag FIFO. ------------------------------------------------------------------------------ Version = 5.2-5F Version Names: fmt_s52-5f_fesim.bin Changes: Fixed a bug in the Link Decoder in the Data Overflow Limit logic. In prior versions, the serial data decoding state machine did not go into the "Wait for Trailer" state at the appropriate time. Added a Link Diagnostic FIFO to capture incoming data streams. ------------------------------------------------------------------------------ Version = 5.2-0F Version Names: fmt_s52-0f_fesim.bin Changes: Reverted to original fmt_s50-Cf_bgc_fesim.bin. Will use as the base going forward. ------------------------------------------------------------------------------ Version = 5.1-5F Version Names: fmt_s51-5f_fesim.bin Changes: Removed L1A gating signal to revert Channel control to the original mode. The Tx loss modification remains so that we can test it without influence of the Channel Enable Gating. ------------------------------------------------------------------------------ Version = 5.1-4F Version Names: fmt_s51-4f_fesim.bin Changes: Fixed bug in L1A gating algorithm. Added Tx loss masking algorithm in FE Decoder block. If Serial Input Shift register fills with all '1's, the decoder will flag the event as Truncated, insert a trailer on the packet, and then wait for the actual trailer to arrive before looking for a new header. This version includes the FE Simulator. ------------------------------------------------------------------------------ Version = 5.1-3F Version Names: fmt_s51-3f_fesim.bin Changes: Fixed bug in L1A gating algorithm Only. ------------------------------------------------------------------------------ Version = 5.1-0F Version Names: fmt_s51-0f_bgc_fesim.bin Changes: Added an L1A Gating signal in all Formatters. Formatter decoders are only enabled after receiving an L1A trigger, and then disabled when all events have been sent from the FMTs. The L1A counter increments when a trigger is detected and decremented when the token is passed from the Formatter. The status can be monitored in Register 0x0040xxF0. Bit 15 is the Decoder Enabled bit, and Bits [14:0] indicate the current L1A count on each Formatter. ------------------------------------------------------------------------------ Version = 5.0-CF Version Names: fmt_s50-Cf_bgc_fesim.bin Changes: Best working version ------------------------------------------------------------------------------ Version = 5.0-7F Version Names: fmt_s50-7f_bgc_fesim.bin Changes: Changed Formatter FE Link Mask interaction with Link FIFO read counter to allow correct monitoring of the FIFO Occupancy Counter ------------------------------------------------------------------------------ Version = 5.0-6F Version Names: fmt_s50-6f_bgc_fesim.bin Changes: Added FE Link Mask triggered exit from the FIFO Readout Controller State Machine in the "Read Out Link FIFO" State to prevent the token getting stuck on any one link during data readout. Returned the control of the Link Mask Disable signal to ECR trigger ------------------------------------------------------------------------------ Version = 5.0-5F Version Names: fmt_s50-5f_bgc_fesim.bin Changes: Link Mask disabled after receiving L1A only ------------------------------------------------------------------------------ Version = 5.0-4F Version Names: fmt_s50-4f_bgc_fesim.bin Changes: Link Mask disabled after receiving ECR only. Changed Data OverFlow Limit default to 0x1C0 (384 hits) ------------------------------------------------------------------------------ Version = 5.0-3F Version Names: fmt_s50-3f_bgc_fesim.bin Changes: Link Mask disabled after receiving and ECR then an L1A. Modified the Link FIFO Readout State Machine to only aloow disable or masking after passing the readout token. ------------------------------------------------------------------------------ Version = 5.0-0F Version Names: fmt_s50-0f_bgc_fesim.bin Changes: Added new link data compression type in decoder block per proposal by Bruce Gallop. Packs up to 16 consecutive hits into each half word in the event data stream. ------------------------------------------------------------------------------ Version = 3.9F to 4.DF 2009 to 2012 Version Names: fmt_s4Df-4.bin, fmt_s4Df-4-fesim.bin (built with FE Sim Changes: In general all changes involved work in and around the Link Decoder FIFO Readout State Machine to improve the SCT Formatter's immunity to corrupted and noisy module data at high rates. There were also fixes to the trailer detection algorithm and improvement to the handling of link timeouts for operation at high trigger rates. The current best operating version is fmt_s4D-4f.bin ------------------------------------------------------------------------------ Version = 3.8F Sept 25th 2009 Changes: First working version of the Time Bin Pipeline stuck bit mask. Tested with scans and with the stuck bit calibration test. The mask appeared to have trouble with the nMask scan, but we think that the issue was due to the configuration streams on the RCF to FMT command interface. We need to test this with a new RCF. ------------------------------------------------------------------------------ Version = 3.6F/3.7F Sept 24th 2009 Changes: First attempts to implement the Time Bin Pipeline stuck bit mask. Neither worked well. ------------------------------------------------------------------------------ Version = 3.5F May 26th 2009 Changes: More minor changes and modifications to the FE Sim block ------------------------------------------------------------------------------ Version = 3.4F May 26th 2009 Changes: Minor changes and modifications to the FE Sim block ------------------------------------------------------------------------------ Version = 3.3F May 26th 2009 Changes: Cleaned up FIFO Readout Control bugs in the Masked link mode. The implementation allowed an unmasked link readout with no hits to appear masked. ------------------------------------------------------------------------------ Version = 3.2F Changes: Added link masking mechanism and datastream error indicator that the MDSP has masked an active link. The new link mask register is located at 0x0040nn28, and the default setting is '0'. When '1' is to bits[11:0] (maps to Links [11:0]), the link decoder will stop capturing data, the link FIFO will be flushed, and a HT word with an error flag will be transmitted to the EFB for each trigger received on the ROD. ------------------------------------------------------------------------------ Version = 3.1F Changes: Implemented fixes to the simulator block - TB input ------------------------------------------------------------------------------ Version = 3.0F Changes: Implemented single FSCT simulator code from TB. Single sim >> FPGA 71% ------------------------------------------------------------------------------ Version = 2.FF Changes: Added FE_DECODER signals to test output ports. FSCT Simulator OK. Full Simulator >> FPGA 91% ------------------------------------------------------------------------------ Version = 2.EF Changes: Fixed an issue in the Link FIFO Readout controller that caused the SCT ROD to stop transmitting data during some calibrations. Testing to validate is still required. Modified Trailer error flag implementation in link decoder block to link the trailer error flag directly to the error detection bit. ------------------------------------------------------------------------------ Version = 2.BF Changes: Fixed an issue in the Link FIFO Readout controller that caused the SCT ROD to gradually lose event sychronization with the combine detector run. The Readout Time Out counter was incrementing when data was stored in the link FIFO waiting for the link trailer to arrive from the modules. Changed the enable counter signal to stop the time out counter if waiting for data while the FIFO is not empty. ------------------------------------------------------------------------------ Version = 2.AF Changes: Fixed the raw data output mode in the link formatter. The chip and channel was lost when the decoder switched over to raw data output mode ------------------------------------------------------------------------------ Version = 2.9F Changes: Added logic to link decoder block to truncate the links that cause the decoders to fall into Raw Data output mode. If a module outputs a data stream that causes a Formatter link to fall into Raw Data Mode, then the link decoder for that specific link will allow a minimum of 2 raw data words in the event stream before truncating the event with a trailer with an error (0x4400). At this point, the link decoder will continue to process the data stream, masking FIFO WEN, until a trailer is detected. If a trailer does not arrive, the link will send timeout words as required by the trigger rate. If a trailer is detected, the link decoder will return to the standard mode of operation. ------------------------------------------------------------------------------ Version = 2.8F Changes: Added ROC state machine change from version V2.5F ------------------------------------------------------------------------------ Version = 2.7F Changes: Added the Serial Decoder bug fix from V2.5F and Register Block modifications that suppress repeats in the upper half data word of the internal registers. ------------------------------------------------------------------------------ Version = 2.6F Changes: Reverted to original version 2.4F VHDL ------------------------------------------------------------------------------ Version = 2.5F Changes: Modified ROC state machine to not allow a timeout after a link has started to play an event. If an event is in the FIFO, then a trailer or data overflow are the only 2 states that can follow. Found and fixed a bug in the serial decoder. If a module puts out a header and then follows with no more data, the decoder would not write a trailer to the link FIFO. This condition would cause the ROC to go into a wait for data state that could only be recovered with a timeout. Reduced FE Module TimeOut Counter increment to 25ns and increased TO limit register from 8 bits to 16 bits. Set timeout limit to 12.8us. ------------------------------------------------------------------------------ Version = 2.4F Changes: Modified FIFO Readout State Machine to fix data readout bug. Added 1 clock extra to the Formatter Enabled signal. The Token passing timing remained the same. Reduced FE Module TimeOut Counter increment to 25ns ------------------------------------------------------------------------------ Version = 2.3F Changes: Added BOC Scan Registers to 0x00400090 to 0x0040009C BOC SCAN Registers: 0x00400090 ==> Control 0x00400094 ==> Global Counter Load Value & Current Count Ox00400098 ==> Bit counters for Links 1 & 0 Ox0040009C ==> Bit counters for Links 3 & 2 Ox004000A0 ==> Bit counters for Links 5 & 4 Ox004000A4 ==> Bit counters for Links 7 & 6 Ox004000A8 ==> Bit counters for Links 9 & 8 Ox004000AC ==> Bit counters for Links 11 & 10 To operate: 1. Set Global Counter Value in bits [15:0] of 0x00400094 This value is only loaded to the global counter if the boc scan engine is in reset (Enable Bit low). 2. Set the Enable Bit to value 1. If the input mux on the ROD is routing signals to the Formatters, then data will cause the data link counter to increment. When the value in the Current Count location (Bits [31:16] of 0x00400094) is equal to 0, the link bit1 counters will stop looking at the data stream. 3. The clear the data link counters, clear the Enable Bit. This does not reset the Global Count Load value ------------------------------------------------------------------------------ Version = 2.2F Changes: Added logic to pause the link decoder for 17 clocks if configuration data is detected in the event data. The configuration data word will be decoded in the event as a FE chip error with a code=7. ------------------------------------------------------------------------------ Version = 2.1F Changes: Removed "101010" as a valid header from the Link Formatter Block Removed "AAAA...." filler word from used register map addresses. ------------------------------------------------------------------------------ Version = 2.0F Changes: Built design from s20e vhdl, changed constant E to F in the Reg Block