------------------------------------------------------------------------------- Atlas SiROD Pixel Formatter VHDL Revision History ------------------------------------------------------------------------------- Version = 4.5F-4 6/09/2016 Changes: Added ECR Flush logic, remapped 160Mb/s FE Simulator links to match new system changes ------------------------------------------------------------------------------- Version = 4.4F-8 10/09/2015 Changes: Modified the logic in the FIFO-Readout-Controller to prevent the Readout token from getting dropped during a Manual Recovery of Link Reset ------------------------------------------------------------------------------- Version = 4.4F-0,1,2,3 9/21/2015 Changes: Incremental changes to recover Calibration ad TimeOut functionality of the Pixel Formatter and include the new diagnostic registers. ------------------------------------------------------------------------------- Version = 4.3F-6 8/28/2015 Changes: Added ECR Flush signal to Master Trigger Counter and ModeBit FIFO block to provide complete reset when ECR Flush bit is enabled ------------------------------------------------------------------------------- Version = 4.3F-1 8/7/2015 Changes: Added Formatter Debug/Status Counters The Control Register is 0x004000FC Bit 1 == Reset when set high, Bit 0 == Enable when set high, and hold when set low. The counters start at 0x00400100, all are 32 bit 0x100 MOD0 ECR Counter 0x104 MOD0 HitWord Count 0x108 MOD0 Event Count 0x10C MOD0 Error Count 0x110 MOD0 Data Proc Count 0x114 MOD0 Clk Count 0x118 TBD 0x11C TBD 0x120 MOD1 ECR Counter 0x124 MOD1 HitWord Count 0x128 MOD1 Event Count 0x12C MOD1 Error Count 0x130 MOD1 Data Proc Count 0x134 MOD1 Clk Count 0x138 TBD 0x13C TBD 0x140 MOD2 ECR Counter 0x144 MOD2 HitWord Count 0x148 MOD2 Event Count 0x14C MOD2 Error Count 0x150 MOD2 Data Proc Count 0x154 MOD2 Clk Count 0x158 TBD 0x15C TBD 0x160 MOD2 ECR Counter 0x164 MOD2 HitWord Count 0x168 MOD2 Event Count 0x16C MOD2 Error Count 0x170 MOD2 Data Proc Count 0x174 MOD2 Clk Count 0x178 TBD 0x17C TBD ------------------------------------------------------------------------------- Version = 4.2F-1 8/5/2015 Changes: Added ChipHasToken signal to the TokenOut signal when the FIFO Readout State Machine is held in "Link Off". ------------------------------------------------------------------------------- Version = 4.2F-0 7/2015 Changes: First Pixel Formatter version that flushes all FIFOs when an ECR arrives. The feature is enabled by setting bits in register 0x0040nn04 that correspond to the FE input links. ------------------------------------------------------------------------------- Version = 4.1F-9 5/2015 Changes: Changed the mapping of the input links to match new changes in the 160MHz interface. ------------------------------------------------------------------------------- Version = 4.0F & 4.1F During 2010 Changes: All version of FMT VHDL during this period were directed at incremental improvements to the MCC Skipped event algorithm operation. The best working version is fmt_p41-8f.bin. ------------------------------------------------------------------------------- Version = 3.FF 17 Dec 2009 Changes: Redesigned MCC Skipped event algorithm to improve the identification and decoding of corrupted events transmitted from the MCC. Tested OK with all simulation data sets on hand, including 5 L1 triggers spaced by 10 to 90 BC, each stretched to 8 accepts (BC). Modes to complete: MCC Skipped code = F, verify function and add a flag ------------------------------------------------------------------------------- Version = 3.EF 27 Sept 2009 Changes: Modified the MCC skipped Event Algorithm to handle the event variances that we have noticed in the MCC. Introduced a minor version number in the code version. This implementation of the PXL formatter was tested with modules in SR1 and various trigger patterns. The -7 version includes a counter to keep track of the number of time that MCC sent a pattern that required forced resynchronization and also includes the first attempt to properly handle the case where the MCC has overflowed and can not send the correct number of skipped events. ------------------------------------------------------------------------------- Version = 3.DF 26 Sept 2009 Changes: Modified the MCC Skipped event algorithm to handle new cases found during data taking. This version solved one specific issue with an extra event sent by the MCC, but uncovered a few new issues. ------------------------------------------------------------------------------- Version = 3.CF 05 May 2009 Changes: Changed RBL default value to 0x780 ------------------------------------------------------------------------------- Version = 3.BF 06 Apr 2009 Changes: Modified simulator by removing static hit data location variable in readout FSM. Reverted send header case back to original version. ------------------------------------------------------------------------------- Version = 3.AF 03 Apr 2009 Changes: Changed simulator code back to the version from fmt_p30F. ------------------------------------------------------------------------------- Version = 3.9F 22 Jan 2009 Changes: Added the Pixel Simulator back into the design. This version is the original Simulator version by JD and DD with the exception of a new event id FIFO that was built without the Core Generator. ------------------------------------------------------------------------------- Version = 3.8F 21 Jan 2009 Changes: Modified MCC Skipped Event implementation for cases when the mcc_skipped counter reaches 0 before the NA counter reaches NA set. If the next has an mcc_skipped flag OR if the L1ID is equal to the current L1ID then the state amchine returns to the readout mode, else it adds another EEH/T and tests again. ------------------------------------------------------------------------------- Version = 3.7F 20 Jan 2009 Changes: More bug fixes to the MCC Skipped Event implementation. Modified the 2048x32 FIFO to handle an edge case where the MCC skip events start when the link FIFO only has 1 trailer in the queue. ------------------------------------------------------------------------------- Version = 3.6F 20 Jan 2009 Changes: Changed default value of the TimeOut register to 0x800 (51.6us). A PixROD with 26 modules will require 1.3ms to process TO events for all links (~750Hz). This value can probably be reduced in the future. ------------------------------------------------------------------------------- Version = 3.5F 19 Jan 2009 Changes: More changes to 2048x32 FIFO block to work on MCC Skipped mode. Passes all timing tests in simulation and event data mashups are gone for all current input cases. Still need to test on modules ------------------------------------------------------------------------------- Version = 3.4F 19 Jan 2009 Changes: More changes to 2048x32 FIFO block to work on MCC Skipped mode. Still has problems with L1ID counting and event data mashup. ------------------------------------------------------------------------------- Version = 3.3F 18 Jan 2009 Changes: More changes to the 2048x32 FIFO block to improve the operation of the MCC skipped event mode in the Formatter. Actual MCC data was used to verify the logic level simulation of the design. There are still a few issues to discuss with regard to data handling. The Pixel simulator is not implemented in this version ------------------------------------------------------------------------------- Version = 3.2F Changes: Fixed the readout controller timeout bug that caused many 0 words to be transmitted up the S-Link. ------------------------------------------------------------------------------- Version = 3.1F Changes: Replaced V30F 160MHz input mapping with code from V19F. Test results will be used to determine the final 160MHz input mapping. Discovered bug in 1BC readouts, in all version back to and including 2.EF ------------------------------------------------------------------------------- Version = 3.0F Changes: Fixed bug in the 80MHz decoder that inserted 1 Raw Data word into each Header/Trailer packet with no hits. After extracting the event ID data, the state machine did not have the logic implemented to wait for a trailer (as in V19F). ------------------------------------------------------------------------------- Version = 2.FF Changes: Fixed bug in 2048x32FIFO, MCC Skipped event mode that caused the L1ID value to increment by 1 when the BCID value crossed the "FF" to "00" threshold. ------------------------------------------------------------------------------- Version = 2.EF Changes: Implemented modifications to the link FIFO to ROC interface that fixed readout bugs that prevented full operation of MCC Skipped Event feature. The ROC will now start a readout when a full event has been skipped by the MCC. ------------------------------------------------------------------------------- Version = 2.DF Changes: Modified FIFO readout to prevent MCC Skipped event readout mode when Formatter is configured for raw data capture. Release date of the .bin file is 23/10/2008. ------------------------------------------------------------------------------- Version = 2.CF Changes: Fixed the issue with the MCC skipped event algorithm, but it has only been tested minimally so far. More thorough test is required before release. Most of the changes were to 2048x32_fifo.vhd. This release also includes the Pixel Simulator block and has added connections to the FE CMD generator in the RCF so that actual L1A, ECR and BCR commands are used by all of the input channel to maintain sychronization. The MCC skipped event configuration requires that the sum of the NA and MCC skipped event fields in the Simulator config register is equal to the NA value in the Formatter NA_ACCEPT register. Hit data will always appear in the middle BC of any stretched trigger event. Also, after a board reset, hit data does not always appear in the events. I think that it is due to the handling of reset states in some of the simulator blocks. When the TIM is used as the trigger source for the ROD, 0xFFh is the BCID offset value used in the EFB to prevent error flags during ID checks. ------------------------------------------------------------------------------- Version = 2.BF Changes: Modified the output data format in 80MHz raw data capture mode to report all bits arriving from a module, including the first edge detected. ------------------------------------------------------------------------------- Version = 2.AF Changes: Continued work to fix MCC Skipped Event readout mode. Addedd 1 clock of extra delay between the transition from Module data and MCC skipped event insertion. Modified the output data format in 40MHz raw data capture mode to report all bits arriving from a module, including the first edge detected. ------------------------------------------------------------------------------- Version = 2.9F Changes: Continued work to fix MCC Skipped Event readout mode. Changed the structure of the Link FIFO control state machine in fifo_2046x32.vhd. ------------------------------------------------------------------------------- Version = 2.8F Changes: Continued work to fix MCC Skipped Event readout mode. ------------------------------------------------------------------------------- Version = 2.7F Changes: Continued work to fix MCC Skipped Event readout mode, concentrating on the dropped trailer. The inserted BCID values are correct in this version. ------------------------------------------------------------------------------- Version = 2.6F Changes: Continued work to fix MCC Skipped Event readout mode. Restored design to V2.3F and looked at the link decoder FIFO as the source for inserted events. In this version the inserted BCID values were calculated incorrectly and in certain cases, one link trailer would be dropped from an event ------------------------------------------------------------------------------- Version = 2.5F Changes: Continued work to fix MCC Skipped Event readout mode. Again, modifications to the FIFO Readout controller did not work properly. This version should not be used. ------------------------------------------------------------------------------- Version = 2.4F Changes: Started work to fix MCC Skipped Event readout mode. Modifications to the FIFO Readout controller did not work properly. This version should not be used. ------------------------------------------------------------------------------- Version = 2.3F Changes: Modified the 40MHz and 80MHz raw data capture modes to minimize the data captured if the Formatter detects a data link sync error during Physics Data Taking mode. If the link decoder detects a sync bit error, then the channel will switch to Raw Data Capture mode, and write 1 word to the link FIFO. After storing 1 word, the link decoder will wait for a trailer to arrive. To maintain the required readout BW, the timeout error counter value should be set to an appropriate value to guarantee that all TO error events can clear the Formatter in the time allowed by the trigger rate. Modified the MCC Empty/Skipped Event algorithm to match the MCC requirement. If the MCC sends an empty event flag, then the ROD will the correct number of LV1 events to maintain system synchronization. If the MCC is operating in consecutive LV1 mode, the ROD will indicate the number of lost consecutive LV1 triggers in one header/trailer word for each TTC LV1 trigger. ------------------------------------------------------------------------------- Version = 2.1F & 2.2F Bypassed ------------------------------------------------------------------------------- Version = 2.0F Changes: Modified Raw Data Capture to start on the first rising edge detected in the decoder when the Formatter is set to capture raw data. ------------------------------------------------------------------------------- Version = 1.FF Changes: Disabled all input links at startup (modified in 1Df and 1Ef for simulation). ------------------------------------------------------------------------------- Version = 1.EF Changes: Added raw data mode to 80MHz decoder. ------------------------------------------------------------------------------- Version = 1.EF Changes: Added raw data mode to 80MHz decoder ------------------------------------------------------------------------------- Version = 1.DF Changes: Reverted to all decoders from version p1Bf. ------------------------------------------------------------------------------- Version = 1.CF Changes: Added raw data modes to all decoders and fixed MCC empty event block. Functioned OK in sim, but not when running scans. ------------------------------------------------------------------------------- Version = 1.BF Changes: Added forced Raw Data mode to 40MHz Link Decoders only, fixed header error and trailer detect bugs in link_formatter_d40.vhd ------------------------------------------------------------------------------- Version 1.AF Changes: Fixed Empty Events bug in FIFO Readout Controller. The algorithm did send out more than 1 empty event per cycle. Changed FIFO Readout Controller algorithm to push out N events per cycle during MCEEV. Changed input map of links into the QUAD-LINK-FORMATTER block. Modified Half-Clock Header valid algorithm. ------------------------------------------------------------------------------- Version 1.9F Changes: Modified 160 and 80MHz link mapping per AK in the QUAD-LINK-FORMATTER block. ------------------------------------------------------------------------------- Version 1.8F Changes: Added bit to register FMT_EDGE_MODE_EN(fmt) (0x0040000C...) to mask Header Errors for pattern "111101" if the FE modules are in Half Clock Mode. Built with ISE8.2i SP3 ------------------------------------------------------------------------------- Version 1.7F Changes: Removed Header Error detect bit from headers "111101" to allow clk/2 mode for input links. Built with ISE8.2i SP3 ------------------------------------------------------------------------------- Version = 1.6F Changes: Removed FE Input Mask and Shift Registers in top_fpix. This was used To mask an input signal from and LVDS driver that was not set up with Fail-safe input protection. This is not required because the with optical BOC in the system, the idle inputs are alway pulled low. ------------------------------------------------------------------------------- Version = 1.5F Changes: Added BOC Scan Registers to 0x00400090 to 0x0040009C BOC SCAN Registers in Formatter 0: (For other locations use 0x400 offset per Formatter) 0x00400090 ==> Control 0x00400094 ==> Global Counter Load Value & Current Count Ox00400098 ==> Bit counters for Links 1 & 0 Ox0040009C ==> Bit counters for Links 3 & 2 To operate: 1. Set Global Counter Value in bits [15:0] of 0x00400094 This value is only loaded to the global counter if the boc scan engine is in reset (Enable Bit low). 2. Set the Enable Bit to value 1. If the input mux on the ROD is routing signals to the Formatters, then data will cause the data link counter to increment. When the value in the Current Count location (Bits [31:16] of 0x00400094) is equal to 0, the link bit1 counters will stop looking at the data stream. 3. The clear the data link counters, clear the Enable Bit. This does not reset the Global Count Load value Thanks to Jens Dopke for the idea and implementation descriptions ------------------------------------------------------------------------------- Version = 1.4F Changes: Link Mapping Change that became the final choice. ------------------------------------------------------------------------------- Version = 1.3F Changes: Inserted 160MHz link map from v10f. ------------------------------------------------------------------------------- Version = 1.2F Changes: Removed "ED" from Header word with a sync bit error and the 80MHz barrel shifter ------------------------------------------------------------------------------- Version = 1.1F Changes: Remapped 80 & 160 MHz inputs to quad-link wrapper block ------------------------------------------------------------------------------- Version = 1.0F Changes: Added preconditioning shift register to 80MHz decoder to allow correct operation on unstable input sources. Added input link masks to disable an input that is stuck at 1. 1) Beginning in Code Version 2.0, the Output data format has been changed to make checking by sight easier.\ Hit data format => 100xFFFFTTTTTTTTxxxCCCCCRRRRRRRR F = FE Chip Number R = Row Number C = Column Number T = TOT Value FE Flag Error (Old) => 0000FFFFxxxxxxxxxxx11110FFFFEEEE FE Flag Error (New) => 0001FFFFxxx11111eeeeeeeeEEEEEEEE 1) ALL signals are positive logic! ... that is, the vhdl code and test benches do not conform to to the top entity signal names.